Istvan Csomortani 7960b00684 block_design: Update with new clock net variables ... Using the new clock net variables in all Xilinx block designs.		2019-06-11 18:13:06 +03:00
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daq2_bd.tcl	block_design: Update with new clock net variables	2019-06-11 18:13:06 +03:00
daq2_qsys.tcl	daq2:qsys: use bundled AXIS interface	2019-05-16 13:27:19 +03:00
daq2_spi.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00