20c714eccf
For all the Xilinx base design, define three global clock nets, which are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk and $sys_iodelay_clk. These clock nets are connected to different clock sources depending of the FPGA architecture used on the carrier. In general the following frequencies are used: - sys_cpu_clk - 100MHz - sys_dma_clk - 200MHz or 250Mhz - sys_iodelay_clk - 200MHz or 500Mhz |
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| .. | ||
| zc706_plddr3_adcfifo_bd.tcl | ||
| zc706_plddr3_constr.xdc | ||
| zc706_plddr3_dacfifo_bd.tcl | ||
| zc706_plddr3_mig.prj | ||
| zc706_system_bd.tcl | ||
| zc706_system_constr.xdc | ||