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Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 		2019-06-11 18:13:06 +03:00
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adrv9371x_bd.tcl block_design: Update with new clock net variables 2019-06-11 18:13:06 +03:00
adrv9371x_qsys.tcl adrv9371:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00