568 lines
18 KiB
Verilog
568 lines
18 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adrv9001 #(
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parameter ID = 0,
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parameter CMOS_LVDS_N = 0,
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parameter TDD_DISABLE = 0,
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parameter DDS_DISABLE = 0,
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parameter INDEPENDENT_1R1T_SUPPORT = 1,
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parameter COMMON_2R2T_SUPPORT = 1,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter USE_RX_CLK_FOR_TX = 0
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) (
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input ref_clk,
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input mssi_sync,
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input tx_output_enable,
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// physical interface
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input rx1_dclk_in_n_NC,
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input rx1_dclk_in_p_dclk_in,
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input rx1_idata_in_n_idata0,
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input rx1_idata_in_p_idata1,
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input rx1_qdata_in_n_qdata2,
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input rx1_qdata_in_p_qdata3,
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input rx1_strobe_in_n_NC,
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input rx1_strobe_in_p_strobe_in,
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input rx2_dclk_in_n_NC,
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input rx2_dclk_in_p_dclk_in,
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input rx2_idata_in_n_idata0,
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input rx2_idata_in_p_idata1,
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input rx2_qdata_in_n_qdata2,
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input rx2_qdata_in_p_qdata3,
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input rx2_strobe_in_n_NC,
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input rx2_strobe_in_p_strobe_in,
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output tx1_dclk_out_n_NC,
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output tx1_dclk_out_p_dclk_out,
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input tx1_dclk_in_n_NC,
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input tx1_dclk_in_p_dclk_in,
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output tx1_idata_out_n_idata0,
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output tx1_idata_out_p_idata1,
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output tx1_qdata_out_n_qdata2,
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output tx1_qdata_out_p_qdata3,
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output tx1_strobe_out_n_NC,
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output tx1_strobe_out_p_strobe_out,
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output tx2_dclk_out_n_NC,
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output tx2_dclk_out_p_dclk_out,
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input tx2_dclk_in_n_NC,
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input tx2_dclk_in_p_dclk_in,
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output tx2_idata_out_n_idata0,
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output tx2_idata_out_p_idata1,
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output tx2_qdata_out_n_qdata2,
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output tx2_qdata_out_p_qdata3,
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output tx2_strobe_out_n_NC,
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output tx2_strobe_out_p_strobe_out,
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output rx1_enable,
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output rx2_enable,
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output tx1_enable,
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output tx2_enable,
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input delay_clk,
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// user interface
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output adc_1_clk,
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output adc_1_rst,
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output adc_1_valid_i0,
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output adc_1_enable_i0,
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output [15:0] adc_1_data_i0,
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output adc_1_valid_q0,
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output adc_1_enable_q0,
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output [15:0] adc_1_data_q0,
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output adc_1_valid_i1,
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output adc_1_enable_i1,
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output [15:0] adc_1_data_i1,
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output adc_1_valid_q1,
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output adc_1_enable_q1,
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output [15:0] adc_1_data_q1,
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input adc_1_dovf,
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output adc_2_clk,
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output adc_2_rst,
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output adc_2_valid_i0,
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output adc_2_enable_i0,
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output [15:0] adc_2_data_i0,
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output adc_2_valid_q0,
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output adc_2_enable_q0,
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output [15:0] adc_2_data_q0,
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input adc_2_dovf,
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output dac_1_clk,
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output dac_1_rst,
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output dac_1_valid_i0,
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output dac_1_enable_i0,
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input [15:0] dac_1_data_i0,
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output dac_1_valid_q0,
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output dac_1_enable_q0,
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input [15:0] dac_1_data_q0,
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output dac_1_valid_i1,
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output dac_1_enable_i1,
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input [15:0] dac_1_data_i1,
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output dac_1_valid_q1,
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output dac_1_enable_q1,
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input [15:0] dac_1_data_q1,
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input dac_1_dunf,
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output dac_2_clk,
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output dac_2_rst,
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output dac_2_valid_i0,
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output dac_2_enable_i0,
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input [15:0] dac_2_data_i0,
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output dac_2_valid_q0,
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output dac_2_enable_q0,
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input [15:0] dac_2_data_q0,
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input dac_2_dunf,
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// TDD interface
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input tdd_sync,
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output tdd_sync_cntr,
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input gpio_rx1_enable_in,
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input gpio_rx2_enable_in,
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input gpio_tx1_enable_in,
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input gpio_tx2_enable_in,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot
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);
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localparam SEVEN_SERIES = 1;
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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localparam DRP_WIDTH = FPGA_TECHNOLOGY == ULTRASCALE ? 9 :
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FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? 9 : 5;
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localparam NUM_LANES = CMOS_LVDS_N ? 5 : 3;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [15:0] rx1_data_i;
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wire [15:0] rx1_data_q;
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wire rx1_data_valid;
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wire rx1_single_lane;
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wire rx1_sdr_ddr_n;
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wire [15:0] rx2_data_i;
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wire [15:0] rx2_data_q;
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wire rx2_data_valid;
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wire rx2_single_lane;
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wire rx2_sdr_ddr_n;
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wire [15:0] tx1_data_i;
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wire [15:0] tx1_data_q;
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wire tx1_data_valid;
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wire tx1_single_lane;
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wire tx1_sdr_ddr_n;
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wire [15:0] tx2_data_i;
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wire [15:0] tx2_data_q;
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wire tx2_data_valid;
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wire tx2_single_lane;
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wire tx2_sdr_ddr_n;
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wire adc_1_valid;
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wire adc_2_valid;
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wire dac_1_valid;
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wire dac_2_valid;
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// internal clocks & resets
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wire up_rstn;
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wire up_clk;
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// clock/reset assignments
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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wire [NUM_LANES-1:0] up_rx1_dld;
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wire [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata;
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wire [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata;
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wire [NUM_LANES-1:0] up_rx2_dld;
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wire [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata;
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wire [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata;
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wire delay_rx1_rst;
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wire delay_rx2_rst;
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wire delay_rx1_locked;
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wire delay_rx2_locked;
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wire [31:0] adc_clk_ratio;
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wire [31:0] dac_clk_ratio;
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axi_adrv9001_if #(
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.NUM_LANES (NUM_LANES),
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.DRP_WIDTH (DRP_WIDTH),
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.IO_DELAY_GROUP (IO_DELAY_GROUP),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
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) i_if(
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//
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// Physical interface
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//
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.ref_clk (ref_clk),
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.mssi_sync (mssi_sync),
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.tx_output_enable (tx_output_enable),
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.rx1_dclk_in_n_NC (rx1_dclk_in_n_NC),
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.rx1_dclk_in_p_dclk_in (rx1_dclk_in_p_dclk_in),
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.rx1_idata_in_n_idata0 (rx1_idata_in_n_idata0),
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.rx1_idata_in_p_idata1 (rx1_idata_in_p_idata1),
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.rx1_qdata_in_n_qdata2 (rx1_qdata_in_n_qdata2),
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.rx1_qdata_in_p_qdata3 (rx1_qdata_in_p_qdata3),
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.rx1_strobe_in_n_NC (rx1_strobe_in_n_NC),
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.rx1_strobe_in_p_strobe_in (rx1_strobe_in_p_strobe_in),
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.rx2_dclk_in_n_NC (rx2_dclk_in_n_NC),
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.rx2_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in),
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.rx2_idata_in_n_idata0 (rx2_idata_in_n_idata0),
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.rx2_idata_in_p_idata1 (rx2_idata_in_p_idata1),
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.rx2_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2),
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.rx2_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3),
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.rx2_strobe_in_n_NC (rx2_strobe_in_n_NC),
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.rx2_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in),
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.tx1_dclk_out_n_NC (tx1_dclk_out_n_NC),
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.tx1_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out),
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.tx1_dclk_in_n_NC (tx1_dclk_in_n_NC),
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.tx1_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in),
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.tx1_idata_out_n_idata0 (tx1_idata_out_n_idata0),
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.tx1_idata_out_p_idata1 (tx1_idata_out_p_idata1),
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.tx1_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2),
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.tx1_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3),
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.tx1_strobe_out_n_NC (tx1_strobe_out_n_NC),
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.tx1_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out),
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.tx2_dclk_out_n_NC (tx2_dclk_out_n_NC),
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.tx2_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
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.tx2_dclk_in_n_NC (tx2_dclk_in_n_NC),
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.tx2_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
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.tx2_idata_out_n_idata0 (tx2_idata_out_n_idata0),
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.tx2_idata_out_p_idata1 (tx2_idata_out_p_idata1),
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.tx2_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
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.tx2_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
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.tx2_strobe_out_n_NC (tx2_strobe_out_n_NC),
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.tx2_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
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//
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// Control interface
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//
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// delay interface (for IDELAY macros)
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.delay_clk (delay_clk),
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.delay_rx1_rst (delay_rx1_rst),
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.delay_rx2_rst (delay_rx2_rst),
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.delay_rx1_locked (delay_rx1_locked),
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.delay_rx2_locked (delay_rx2_locked),
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.up_clk (up_clk),
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.up_rx1_dld (up_rx1_dld),
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.up_rx1_dwdata (up_rx1_dwdata),
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.up_rx1_drdata (up_rx1_drdata),
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.up_rx2_dld (up_rx2_dld),
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.up_rx2_dwdata (up_rx2_dwdata),
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.up_rx2_drdata (up_rx2_drdata),
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//
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// Transport layer interface
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//
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// ADC interface
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.adc_clk_ratio (adc_clk_ratio),
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.rx1_clk (adc_1_clk),
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.rx1_rst (adc_1_rst),
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.rx1_data_valid (rx1_data_valid),
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.rx1_data_i (rx1_data_i),
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.rx1_data_q (rx1_data_q),
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.rx1_single_lane (rx1_single_lane),
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.rx1_sdr_ddr_n (rx1_sdr_ddr_n),
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.rx2_clk (adc_2_clk),
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.rx2_rst (adc_2_rst),
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.rx2_data_valid (rx2_data_valid),
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.rx2_data_i (rx2_data_i),
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.rx2_data_q (rx2_data_q),
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.rx2_single_lane (rx2_single_lane),
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.rx2_sdr_ddr_n (rx2_sdr_ddr_n),
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// DAC interface
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.dac_clk_ratio (dac_clk_ratio),
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.tx1_clk (dac_1_clk),
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.tx1_rst (dac_1_rst),
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.tx1_data_valid (tx1_data_valid),
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.tx1_data_i (tx1_data_i),
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.tx1_data_q (tx1_data_q),
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.tx1_single_lane (tx1_single_lane),
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.tx1_sdr_ddr_n (tx1_sdr_ddr_n),
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.tx2_clk (dac_2_clk),
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.tx2_rst (dac_2_rst),
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.tx2_data_valid (tx2_data_valid),
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.tx2_data_i (tx2_data_i),
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.tx2_data_q (tx2_data_q),
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.tx2_single_lane (tx2_single_lane),
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.tx2_sdr_ddr_n (tx2_sdr_ddr_n)
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);
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// common processor control
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axi_ad9001_core #(
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.ID (ID),
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.NUM_LANES (NUM_LANES),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
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.DRP_WIDTH (DRP_WIDTH),
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.TDD_DISABLE (TDD_DISABLE),
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.DDS_DISABLE (DDS_DISABLE),
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.INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT),
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.COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE)
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) i_core (
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// ADC interface
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.rx1_clk (adc_1_clk),
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.rx1_rst (adc_1_rst),
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.rx1_data_valid (rx1_data_valid),
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.rx1_data_i (rx1_data_i),
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.rx1_data_q (rx1_data_q),
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.rx1_single_lane (rx1_single_lane),
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.rx1_sdr_ddr_n (rx1_sdr_ddr_n),
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.rx2_clk (adc_2_clk),
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.rx2_rst (adc_2_rst),
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.rx2_data_valid (rx2_data_valid),
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.rx2_data_i (rx2_data_i),
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.rx2_data_q (rx2_data_q),
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.rx2_single_lane (rx2_single_lane),
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.rx2_sdr_ddr_n (rx2_sdr_ddr_n),
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.adc_clk_ratio (adc_clk_ratio),
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//DAC interface
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.tx1_clk (dac_1_clk),
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.tx1_rst (dac_1_rst),
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.tx1_data_valid (tx1_data_valid),
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.tx1_data_i (tx1_data_i),
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.tx1_data_q (tx1_data_q),
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|
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.tx1_single_lane (tx1_single_lane),
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.tx1_sdr_ddr_n (tx1_sdr_ddr_n),
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|
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.tx2_clk (dac_2_clk),
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.tx2_rst (dac_2_rst),
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.tx2_data_valid (tx2_data_valid),
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.tx2_data_i (tx2_data_i),
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.tx2_data_q (tx2_data_q),
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|
|
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.tx2_single_lane (tx2_single_lane),
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.tx2_sdr_ddr_n (tx2_sdr_ddr_n),
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.dac_clk_ratio (dac_clk_ratio),
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//
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// User layer interface
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//
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.adc_1_valid (adc_1_valid),
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.adc_1_enable_i0 (adc_1_enable_i0),
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.adc_1_data_i0 (adc_1_data_i0),
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.adc_1_enable_q0 (adc_1_enable_q0),
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.adc_1_data_q0 (adc_1_data_q0),
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.adc_1_enable_i1 (adc_1_enable_i1),
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.adc_1_data_i1 (adc_1_data_i1),
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.adc_1_enable_q1 (adc_1_enable_q1),
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.adc_1_data_q1 (adc_1_data_q1),
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.adc_1_dovf (adc_1_dovf),
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|
|
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.adc_2_valid (adc_2_valid),
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.adc_2_enable_i (adc_2_enable_i0),
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.adc_2_data_i (adc_2_data_i0),
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.adc_2_enable_q (adc_2_enable_q0),
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.adc_2_data_q (adc_2_data_q0),
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.adc_2_dovf (adc_2_dovf),
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|
|
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.dac_1_valid (dac_1_valid),
|
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.dac_1_enable_i0 (dac_1_enable_i0),
|
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.dac_1_data_i0 (dac_1_data_i0),
|
|
.dac_1_enable_q0 (dac_1_enable_q0),
|
|
.dac_1_data_q0 (dac_1_data_q0),
|
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.dac_1_enable_i1 (dac_1_enable_i1),
|
|
.dac_1_data_i1 (dac_1_data_i1),
|
|
.dac_1_enable_q1 (dac_1_enable_q1),
|
|
.dac_1_data_q1 (dac_1_data_q1),
|
|
.dac_1_dunf (dac_1_dunf),
|
|
|
|
.dac_2_valid (dac_2_valid),
|
|
.dac_2_enable_i0 (dac_2_enable_i0),
|
|
.dac_2_data_i0 (dac_2_data_i0),
|
|
.dac_2_enable_q0 (dac_2_enable_q0),
|
|
.dac_2_data_q0 (dac_2_data_q0),
|
|
.dac_2_dunf (dac_2_dunf),
|
|
|
|
.delay_clk (delay_clk),
|
|
|
|
.up_rx1_dld (up_rx1_dld),
|
|
.up_rx1_dwdata (up_rx1_dwdata),
|
|
.up_rx1_drdata (up_rx1_drdata),
|
|
.delay_rx1_rst (delay_rx1_rst),
|
|
.delay_rx1_locked (delay_rx1_locked),
|
|
|
|
.up_rx2_dld (up_rx2_dld),
|
|
.up_rx2_dwdata (up_rx2_dwdata),
|
|
.up_rx2_drdata (up_rx2_drdata),
|
|
.delay_rx2_rst (delay_rx2_rst),
|
|
.delay_rx2_locked (delay_rx2_locked),
|
|
|
|
// TDD interface
|
|
.tdd_sync (tdd_sync),
|
|
.tdd_sync_cntr (tdd_sync_cntr),
|
|
.tdd_rx1_rf_en (tdd_rx1_rf_en),
|
|
.tdd_tx1_rf_en (tdd_tx1_rf_en),
|
|
.tdd_if1_mode (tdd_if1_mode),
|
|
.tdd_rx2_rf_en (tdd_rx2_rf_en),
|
|
.tdd_tx2_rf_en (tdd_tx2_rf_en),
|
|
.tdd_if2_mode (tdd_if2_mode),
|
|
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_s),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_s),
|
|
.up_rack (up_rack_s)
|
|
);
|
|
|
|
assign adc_1_valid_i0 = adc_1_valid;
|
|
assign adc_1_valid_q0 = adc_1_valid;
|
|
assign adc_1_valid_i1 = adc_1_valid;
|
|
assign adc_1_valid_q1 = adc_1_valid;
|
|
assign adc_2_valid_i0 = adc_2_valid;
|
|
assign adc_2_valid_q0 = adc_2_valid;
|
|
|
|
assign dac_1_valid_i0 = dac_1_valid;
|
|
assign dac_1_valid_q0 = dac_1_valid;
|
|
assign dac_1_valid_i1 = dac_1_valid;
|
|
assign dac_1_valid_q1 = dac_1_valid;
|
|
assign dac_2_valid_i0 = dac_2_valid;
|
|
assign dac_2_valid_q0 = dac_2_valid;
|
|
|
|
assign rx1_enable = tdd_if1_mode ? tdd_rx1_rf_en : gpio_rx1_enable_in;
|
|
assign rx2_enable = tdd_if2_mode ? tdd_rx2_rf_en : gpio_rx2_enable_in;
|
|
assign tx1_enable = tdd_if1_mode ? tdd_tx1_rf_en : gpio_tx1_enable_in;
|
|
assign tx2_enable = tdd_if2_mode ? tdd_tx2_rf_en : gpio_tx2_enable_in;
|
|
|
|
// up bus interface
|
|
up_axi #(
|
|
.AXI_ADDRESS_WIDTH(15)
|
|
) i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr[14:0]),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr[14:0]),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s[12:0]),
|
|
.up_wdata (up_wdata_s),
|
|
.up_rdata (up_rdata_s),
|
|
.up_wack (up_wack_s),
|
|
.up_raddr (up_raddr_s[12:0]),
|
|
.up_rreq (up_rreq_s),
|
|
.up_rack (up_rack_s)
|
|
);
|
|
|
|
// Alias Rx/Tx peripherals @ 0x8000
|
|
assign up_raddr_s[13] = 1'b0;
|
|
assign up_waddr_s[13] = 1'b0;
|
|
|
|
endmodule
|