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pluto_hdl_adi/library/axi_dmac
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Lars-Peter Clausen 764f31463e axi_dmac: tb: Allow testing asymmetric interface widths 
One of the major features of the DMAC is being able to handle non matching
interface widths for the destination and source side.

Currently the test benches only support the case where the width for the
source and the destination side are the same. Extend them so that it is
possible to also test and verify setups where the width is not the same.

To accomplish this each byte memory location is treated as if it contained
the lower 8 bytes of its address. And then the written/read data is
compared to the expected data based on that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-11-30 23:41:49 +02:00
..
bd axi_dmac: fix address width detection 2018-07-20 18:12:24 +03:00
tb axi_dmac: tb: Allow testing asymmetric interface widths 2018-11-30 23:41:49 +02:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_burst_memory.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_hw.tcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_ip.tcl axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_regmap_request.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_reset_manager.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_resize_dest.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_resize_src.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_response_manager.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_axi_mm.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
request_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00