pluto_hdl_adi/library/altera/avl_dacfifo
Istvan Csomortani 960883c789 avl_dacfifo: Fix dac_xfer_req generation
The dac_xfer_req should indicate one single thing, that the FIFO is in
read phase. Should not be affected by any signals, which indicates data
validity on any interface. (e.g. dac_valid)
This signal is not used by the device core, its main purpose is to
indicate the state of the interface for a posible intermediat processing
module.
2017-11-03 09:32:10 +00:00
..
avl_dacfifo.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_byteenable_coder.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
avl_dacfifo_byteenable_decoder.v license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
avl_dacfifo_constr.sdc avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_hw.tcl avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
avl_dacfifo_rd.v avl_dacfifo: Fix dac_xfer_req generation 2017-11-03 09:32:10 +00:00
avl_dacfifo_wr.v avl_dacfifo: Fix write enable generation 2017-11-01 12:22:18 +00:00
util_dacfifo_bypass.v avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00