Adrian Costina 73ef0fb48c adrv9371x: kcu105: Fix transceiver and clock placement		2018-02-13 17:33:38 +02:00
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a10gx	Make: Update makefiles	2017-11-20 14:27:39 +02:00
a10soc	Make: Update makefiles	2017-11-20 14:27:39 +02:00
common	adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled	2017-10-04 11:29:09 +01:00
kcu105	adrv9371x: kcu105: Fix transceiver and clock placement	2018-02-13 17:33:38 +02:00
zc706	adrv9371: Increase FCLK2 to 200MHz to support max sampling rates	2018-01-09 15:20:06 +01:00
zcu102	adrv9371: Increase FCLK2 to 200MHz to support max sampling rates	2018-01-09 15:20:06 +01:00
Makefile	[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx	2017-09-25 08:56:40 +01:00