161 lines
4.6 KiB
Verilog
161 lines
4.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// serial data output interface: serdes(x8)
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`timescale 1ps/1ps
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module ad_serdes_clk #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter DDR_OR_SDR_N = 1,
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parameter CLKIN_DS_OR_SE_N = 1,
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parameter SERDES_FACTOR = 8,
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parameter MMCM_OR_BUFR_N = 1,
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parameter MMCM_CLKIN_PERIOD = 1.667,
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parameter MMCM_VCO_DIV = 6,
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parameter MMCM_VCO_MUL = 12.000,
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parameter MMCM_CLK0_DIV = 2.000,
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parameter MMCM_CLK1_DIV = 6
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) (
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// clock and divided clock
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input rst,
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input clk_in_p,
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input clk_in_n,
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output clk,
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output div_clk,
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output out_clk,
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output loaden,
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output [ 7:0] phase,
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// drp interface
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input up_clk,
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input up_rstn,
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input up_drp_sel,
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input up_drp_wr,
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input [11:0] up_drp_addr,
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input [31:0] up_drp_wdata,
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output [31:0] up_drp_rdata,
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output up_drp_ready,
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output up_drp_locked
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);
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localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR / 2 : SERDES_FACTOR;
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// internal signals
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wire clk_in_s;
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// defaults
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assign loaden = 'd0;
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assign phase = 'd0;
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assign up_drp_rdata[31:16] = 'd0;
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// instantiations
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generate
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if (CLKIN_DS_OR_SE_N == 1) begin
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IBUFGDS i_clk_in_ibuf (
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.I (clk_in_p),
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.IB (clk_in_n),
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.O (clk_in_s));
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end else begin
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IBUF IBUF_inst (
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.O(clk_in_s),
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.I(clk_in_p));
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end
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endgenerate
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generate
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if (MMCM_OR_BUFR_N == 1) begin
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ad_mmcm_drp #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
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.MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
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.MMCM_VCO_DIV (MMCM_VCO_DIV),
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.MMCM_VCO_MUL (MMCM_VCO_MUL),
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.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
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.MMCM_CLK0_PHASE (0.0),
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.MMCM_CLK1_DIV (MMCM_CLK1_DIV),
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.MMCM_CLK1_PHASE (0.0),
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.MMCM_CLK2_DIV (MMCM_CLK0_DIV),
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.MMCM_CLK2_PHASE (90.0)
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) i_mmcm_drp (
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.clk (clk_in_s),
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.clk2 (1'b0),
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.clk_sel (1'b1),
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.mmcm_rst (rst),
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.mmcm_clk_0 (clk),
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.mmcm_clk_1 (div_clk),
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.mmcm_clk_2 (out_clk),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata[15:0]),
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.up_drp_rdata (up_drp_rdata[15:0]),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked (up_drp_locked));
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end
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endgenerate
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generate
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if (MMCM_OR_BUFR_N == 0) begin
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BUFIO i_clk_buf (
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.I (clk_in_s),
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.O (clk));
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BUFR #(
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.BUFR_DIVIDE(BUFR_DIVIDE)
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) i_div_clk_buf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_in_s),
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.O (div_clk));
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assign out_clk = clk;
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assign up_drp_rdata[15:0] = 'd0;
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assign up_drp_ready = 'd0;
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assign up_drp_locked = 'd0;
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end
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endgenerate
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endmodule
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