pluto_hdl_adi/library/axi_dmac/tb
Lars-Peter Clausen 859e3d2ed1 axi_dmac: Rework data store-and-forward buffer
Currently the DMAC uses a simple FIFO as the store-and-forward buffer. The
FIFO handshaking is beat based whereas the remainder of the DMAC is burst
based. This means that additional control signals have to be combined with
the FIFO handshaking signal to generate the external handshaking signals.

Re-work the store-and-forward buffer to utilize a BRAM that is subdivided
into N segments. Where N is the maximum number of bursts that can be stored
in the buffer and each segment has the size of the maximum burst length.
Each segment stores the data associated with one burst and even when the
burst is shorter than the maximum burst length the next burst will be
stored in the next segment.

The new store-and-forward buffer takes care of generating all the
handshaking signals. This means handshaking is generated in a central place
and does not have to be combined from multiple data-paths simplifying the
overall logic.

The new store-and-forward buffer also takes care of data width up- and
down-sizing in case that the source and sink modules have a different data
width. This tighter integration will allow future enhancements like using
asymmetric memory.

This re-work lays the foundation of future enhancements to the DMA like
support for un-aligned transfers and early transfer abort which would have
been much more difficult to implement with the previous architecture.

In addition it significantly reduces the resource utilization of the
store-and-forward buffer and allows for better timing due to reduced
combinatorial path lengths.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-03 13:44:34 +02:00
..
axi_read_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_slave.v axi_dmac: Add transfer testbenches 2018-05-03 14:49:06 +02:00
axi_write_slave.v axi_dmac/dma_write_tb: added data integrity check 2018-05-03 14:49:06 +02:00
dma_read_shutdown_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_read_shutdown_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_read_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_read_tb.v axi_dmac: Hook up rlast for MM-AXI source interface 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_write_shutdown_tb.v axi_dmac: Add testbenches that exercise DMA shutdown 2018-07-03 13:44:34 +02:00
dma_write_tb axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
dma_write_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
regmap_tb axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00
regmap_tb.v axi_dmac: made vlog pass 2018-05-03 14:49:06 +02:00
reset_manager_tb axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
reset_manager_tb.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
run_tb.sh axi_dmac: added ModelSim support to run_tb.sh 2018-05-03 14:49:06 +02:00
tb_base.v axi_dmac: Add simple register map testbench 2018-05-03 14:49:06 +02:00