137 lines
4.5 KiB
Tcl
137 lines
4.5 KiB
Tcl
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# ip related stuff
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proc adi_ip_create {ip_name} {
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create_project $ip_name . -force
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set proj_dir [get_property directory [current_project]]
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set proj_name [get_projects $ip_name]
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}
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proc adi_ip_files {ip_name ip_files} {
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set proj_fileset [get_filesets sources_1]
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add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
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set_property "top" "$ip_name" $proj_fileset
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}
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proc adi_ip_constraints {ip_name ip_constr_files} {
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set proj_filegroup [ipx::get_file_group xilinx_verilogsynthesis [ipx::current_core]]
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ipx::add_file $ip_constr_files $proj_filegroup
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set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup]
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set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup]
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}
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proc adi_ip_properties {ip_name} {
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ipx::package_project -root_dir .
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ipx::remove_memory_map {s_axi} [ipx::current_core]
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ipx::add_memory_map {s_axi} [ipx::current_core]
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set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]]
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ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]]
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set_property range {65536} [ipx::get_address_block axi_lite \
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[ipx::get_memory_map s_axi [ipx::current_core]]]
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set_property vendor {analog.com} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {Analog Devices} [ipx::current_core]
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set_property company_url {www.analog.com} [ipx::current_core]
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set_property value {0xFFFFFFFF} [ipx::get_hdl_parameter C_HIGHADDR [ipx::current_core]]
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set_property value {0x00000000} [ipx::get_hdl_parameter C_BASEADDR [ipx::current_core]]
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set_property supported_families \
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{{kintexu} {Pre-Production} \
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{virtexu} {Pre-Production} \
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{virtex7} {Production} \
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{qvirtex7} {Production} \
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{kintex7} {Production} \
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{kintex7l} {Production} \
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{qkintex7} {Production} \
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{qkintex7l} {Production} \
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{artix7} {Production} \
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{artix7l} {Production} \
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{aartix7} {Production} \
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{qartix7} {Production} \
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{zynq} {Production} \
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{qzynq} {Production} \
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{azynq} {Production}} \
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[ipx::current_core]
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}
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proc adi_ip_properties_lite {ip_name} {
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ipx::package_project -root_dir .
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set_property vendor {analog.com} [ipx::current_core]
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set_property library {user} [ipx::current_core]
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set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core]
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set_property vendor_display_name {Analog Devices} [ipx::current_core]
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set_property company_url {www.analog.com} [ipx::current_core]
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set_property supported_families \
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{{kintexu} {Pre-Production} \
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{virtexu} {Pre-Production} \
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{virtex7} {Production} \
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{qvirtex7} {Production} \
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{kintex7} {Production} \
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{kintex7l} {Production} \
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{qkintex7} {Production} \
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{qkintex7l} {Production} \
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{artix7} {Production} \
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{artix7l} {Production} \
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{aartix7} {Production} \
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{qartix7} {Production} \
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{zynq} {Production} \
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{qzynq} {Production} \
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{azynq} {Production}} \
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[ipx::current_core]
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}
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proc adi_set_ports_dependency {port_prefix dependency} {
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foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
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set_property ENABLEMENT_DEPENDENCY $dependency $port
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}
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}
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proc adi_set_bus_dependency {bus prefix dependency} {
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set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interface $bus [ipx::current_core]]
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adi_set_ports_dependency $prefix $dependency
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}
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proc adi_add_port_map {bus phys logic} {
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set map [ipx::add_port_map $phys $bus]
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set_property "PHYSICAL_NAME" $phys $map
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set_property "LOGICAL_NAME" $logic $map
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}
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proc adi_add_bus {bus_name bus_type mode port_maps} {
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set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
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if { $bus_type == "axis" } {
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set abst_type "axis_rtl"
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} elseif { $bus_type == "aximm" } {
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set abst_type "aximm_rtl"
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} else {
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set abst_type $bus_type
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}
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set_property "ABSTRACTION_TYPE_LIBRARY" "interface" $bus
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set_property "ABSTRACTION_TYPE_NAME" $abst_type $bus
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set_property "ABSTRACTION_TYPE_VENDOR" "xilinx.com" $bus
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set_property "ABSTRACTION_TYPE_VERSION" "1.0" $bus
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set_property "BUS_TYPE_LIBRARY" "interface" $bus
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set_property "BUS_TYPE_NAME" $bus_type $bus
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set_property "BUS_TYPE_VENDOR" "xilinx.com" $bus
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set_property "BUS_TYPE_VERSION" "1.0" $bus
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set_property "CLASS" "bus_interface" $bus
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set_property "INTERFACE_MODE" $mode $bus
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foreach port_map $port_maps {
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adi_add_port_map $bus {*}$port_map
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}
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}
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