pluto_hdl_adi/projects
Lars-Peter Clausen 669a2da735 common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.

To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-20 19:45:27 +02:00
..
ad5766_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad6676evb Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
ad7616_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad7768evb scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9265_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9434_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9467_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad9739a_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
ad77681evb ad77681evb: Suppress a critical warning 2017-06-22 14:25:43 +01:00
adaq7980_sdz scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
adrv9361z7035 rfsom/ccbox- rtc int 2017-07-20 09:22:45 -04:00
adrv9364z7020 rfsom2/ccbox- rtc int 2017-07-20 09:25:09 -04:00
adrv9371x adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary 2017-07-14 10:20:57 +03:00
adv7511 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
arradio arradio/c5soc- clocking changes 2017-07-20 13:05:07 -04:00
cftl_cip scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
cftl_std scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
cn0363 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
common common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion 2017-07-20 19:45:27 +02:00
daq1 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
daq2 daq2: daq2_qsys.tcl: Use sys_dma_clk 2017-07-17 17:38:20 +02:00
daq3 daq3/zc706: Fix system_top instantiation 2017-07-06 13:29:09 +01:00
fmcadc2 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
fmcadc4 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
fmcadc5 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
fmcjesdadc1 fmcjesdadc1: vc707: Remove unsed mb_intrs signal 2017-07-05 14:38:25 +02:00
fmcomms2 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
fmcomms5 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
fmcomms7 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
fmcomms11 Connect JESD204 interrupts 2017-07-05 14:37:50 +02:00
imageon scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
m2k scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
motcon2_fmc scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
pluto scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
scripts adi_board.tcl: ad_xcvrcon: Add lane mapping support 2017-06-20 17:39:41 +02:00
usb_fx3 scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
usdrx1 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
usrpe31x scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Makefile hdlmake.pl updates 2017-06-15 11:42:44 -04:00