90 lines
3.9 KiB
Tcl
Executable File
90 lines
3.9 KiB
Tcl
Executable File
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package require -exact qsys 13.0
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9680
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set_module_property DESCRIPTION "AXI AD9680 Interface"
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set_module_property VERSION 1.0
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set_module_property DISPLAY_NAME axi_ad9680
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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set_fileset_property quartus_synth TOP_LEVEL axi_ad9680
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add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
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add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
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add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
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add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
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add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
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add_fileset_file up_delay_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_delay_cntrl.v
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add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
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add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
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add_fileset_file axi_ad9680_pnmon.v VERILOG PATH axi_ad9680_pnmon.v
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add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v
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add_fileset_file axi_ad9680_if.v VERILOG PATH axi_ad9680_if.v
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add_fileset_file axi_ad9680.v VERILOG PATH axi_ad9680.v TOP_LEVEL_FILE
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add_fileset_file ad_axi_ip_constr.sdc SDC PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
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# parameters
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add_parameter PCORE_ID INTEGER 0
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set_parameter_property PCORE_ID DEFAULT_VALUE 0
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set_parameter_property PCORE_ID DISPLAY_NAME PCORE_ID
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set_parameter_property PCORE_ID TYPE INTEGER
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set_parameter_property PCORE_ID UNITS None
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set_parameter_property PCORE_ID HDL_PARAMETER true
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# axi4 slave
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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# transceiver interface
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ad_alt_intf clock rx_clk input 1
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ad_alt_intf signal rx_data input 128
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# dma interface
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ad_alt_intf clock adc_clock output 1
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ad_alt_intf signal adc_valid_0 output 1
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ad_alt_intf signal adc_enable_0 output 1
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ad_alt_intf signal adc_data_0 output 64
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ad_alt_intf signal adc_valid_1 output 1
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ad_alt_intf signal adc_enable_1 output 1
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ad_alt_intf signal adc_data_1 output 64
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ad_alt_intf signal adc_dovf input 1
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ad_alt_intf signal adc_dunf input 1
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