Adrian Costina a49eb5853b ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems ... For ZC706 Fixed one constraint which was not correct		2014-08-26 16:28:41 +03:00
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zc706_system_bd.tcl	Zynq Base System: Reset is synchronized to lowest system clock	2014-03-26 17:58:14 +02:00
zc706_system_constr.xdc	ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems	2014-08-26 16:28:41 +03:00
zc706_system_mig.prj	fmcomms5: register map changes	2014-07-08 16:57:43 -04:00
zc706_system_mig_constr.xdc	dmac: create fifo interface to avoid being treated as axi control stream	2014-05-27 10:25:14 -04:00
zc706_system_plddr3.tcl	ad9625_plddr: PL DDR3 fixes	2014-07-23 19:34:44 +03:00