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Lars-Peter Clausen 6ad589475a up_axi: Prevent read and write requests from racing against each other Make sure that if a read and a write request arrive on the very same clock cycle to only accept one of them. The simple solution chosen here is to only accept the write request when this happens and delay the acceptance of the read request until the write request is finished. This solution is not fair since a write request will always take precedence, which in theory allows the write bus to starve the read bus. But in practice we should never see that many write requests that we are unable to answer the read request. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-09-10 13:04:05 +02:00
library	up_axi: Prevent read and write requests from racing against each other	2014-09-10 13:04:05 +02:00
projects	fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock	2014-09-09 15:05:06 +02:00
.gitignore	a5soc: increase pipeline for qsys	2014-05-04 10:38:53 -04:00
LICENSE	…
README.md	Add a link to EngineerZone	2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga