82 lines
3.2 KiB
Tcl
82 lines
3.2 KiB
Tcl
#adaq8092
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create_bd_port -dir I adc_clk_in_p
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create_bd_port -dir I adc_clk_in_n
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#interface port create
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create_bd_port -dir I adc_data_or_p
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create_bd_port -dir I adc_data_or_n
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create_bd_port -dir I -from 6 -to 0 adc_data_in1_p
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create_bd_port -dir I -from 6 -to 0 adc_data_in1_n
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create_bd_port -dir I -from 6 -to 0 adc_data_in2_p
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create_bd_port -dir I -from 6 -to 0 adc_data_in2_n
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# adc peripheral
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ad_ip_instance util_cpack2 axi_adaq8092_cpack [list \
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NUM_OF_CHANNELS 2 \
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SAMPLES_PER_CHANNEL 1 \
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SAMPLE_DATA_WIDTH 16 \
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]
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ad_ip_instance axi_dmac axi_adaq8092_dma
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ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_adaq8092_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_parameter axi_adaq8092_dma CONFIG.AXI_SLICE_DEST 1
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# connections
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#adaq8092_core
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ad_ip_instance axi_adaq8092 axi_adaq8092
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ad_ip_parameter axi_adaq8092 CONFIG.POLARITY_MASK 28'hfffffff
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ad_ip_parameter axi_adaq8092 CONFIG.OUTPUT_MODE 0
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ad_connect adc_clk_in_p axi_adaq8092/adc_clk_in_p
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ad_connect adc_clk_in_n axi_adaq8092/adc_clk_in_n
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ad_connect adc_data_in1_p axi_adaq8092/lvds_adc_data_in1_p
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ad_connect adc_data_in1_n axi_adaq8092/lvds_adc_data_in1_n
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ad_connect adc_data_in2_p axi_adaq8092/lvds_adc_data_in2_p
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ad_connect adc_data_in2_n axi_adaq8092/lvds_adc_data_in2_n
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ad_connect adc_data_or_p axi_adaq8092/lvds_adc_or_in_p
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ad_connect adc_data_or_n axi_adaq8092/lvds_adc_or_in_n
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ad_connect adaq8092_clk axi_adaq8092/adc_clk
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ad_connect $sys_iodelay_clk axi_adaq8092/delay_clk
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#adaq8092_cpack
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ad_connect axi_adaq8092/adc_enable_1 axi_adaq8092_cpack/enable_0
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ad_connect axi_adaq8092/adc_data_channel1 axi_adaq8092_cpack/fifo_wr_data_0
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ad_connect axi_adaq8092/adc_enable_2 axi_adaq8092_cpack/enable_1
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ad_connect axi_adaq8092/adc_data_channel2 axi_adaq8092_cpack/fifo_wr_data_1
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ad_connect axi_adaq8092_dma/fifo_wr axi_adaq8092_cpack/packed_fifo_wr
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ad_connect axi_adaq8092/adc_valid axi_adaq8092_cpack/fifo_wr_en
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ad_connect axi_adaq8092/adc_dovf axi_adaq8092_cpack/fifo_wr_overflow
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ad_connect axi_adaq8092/adc_clk axi_adaq8092_cpack/clk
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ad_connect axi_adaq8092/adc_clk axi_adaq8092_dma/fifo_wr_clk
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ad_connect axi_adaq8092/adc_rst axi_adaq8092_cpack/reset
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# address mapping
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ad_cpu_interconnect 0x44A00000 axi_adaq8092
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ad_cpu_interconnect 0x44A30000 axi_adaq8092_dma
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# interconnect (adc)
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_adaq8092_dma/m_dest_axi
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ad_connect $sys_cpu_resetn axi_adaq8092_dma/m_dest_axi_aresetn
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# interrupts
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ad_cpu_interrupt ps-13 mb-13 axi_adaq8092_dma/irq
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