283 lines
8.6 KiB
Verilog
283 lines
8.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Constraints:
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`timescale 1ns/100ps
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module util_do_ram #(
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parameter SRC_DATA_WIDTH = 512,
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parameter DST_DATA_WIDTH = 128,
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parameter LENGTH_WIDTH = 16
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) (
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input wr_request_enable,
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input wr_request_valid,
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output reg wr_request_ready = 1'b0,
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input [LENGTH_WIDTH-1:0] wr_request_length,
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output reg [LENGTH_WIDTH-1:0] wr_response_measured_length = 'h0,
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output reg wr_response_eot = 1'b0,
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input rd_request_enable,
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input rd_request_valid,
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output rd_request_ready,
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input [LENGTH_WIDTH-1:0] rd_request_length,
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output rd_response_eot,
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// Slave streaming AXI interface
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input s_axis_aclk,
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input s_axis_aresetn,
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output reg s_axis_ready = 1'b0,
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input s_axis_valid,
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input [SRC_DATA_WIDTH-1:0] s_axis_data,
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input [SRC_DATA_WIDTH/8-1:0] s_axis_strb,
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input [SRC_DATA_WIDTH/8-1:0] s_axis_keep,
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input [0:0] s_axis_user,
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input s_axis_last,
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// Master streaming AXI interface
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output m_axis_valid,
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output [DST_DATA_WIDTH-1:0] m_axis_data,
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output [DST_DATA_WIDTH/8-1:0] m_axis_strb,
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output [DST_DATA_WIDTH/8-1:0] m_axis_keep,
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output [0:0] m_axis_user,
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output m_axis_last
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);
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// src = s_axis_* = wr
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// dst = m_axis_* = rd
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//
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localparam RAM_LATENCY = 2;
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localparam SRC_ADDR_ALIGN = $clog2(SRC_DATA_WIDTH/8);
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localparam DST_ADDR_ALIGN = $clog2(DST_DATA_WIDTH/8);
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localparam SRC_ADDRESS_WIDTH = LENGTH_WIDTH - SRC_ADDR_ALIGN;
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localparam DST_ADDRESS_WIDTH = LENGTH_WIDTH - DST_ADDR_ALIGN;
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wire wr_enable;
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wire [DST_DATA_WIDTH-1:0] rd_data;
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wire [1:0] rd_fifo_room;
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wire rd_enable;
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wire rd_last_beat;
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wire rd_fifo_s_ready;
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wire rd_fifo_s_valid;
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reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
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reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
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reg [DST_DATA_WIDTH-1:0] rd_data_l2 = 'h0;
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reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
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reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
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reg rd_pending = 1'b0;
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always @(posedge s_axis_aclk) begin
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if (~s_axis_aresetn)
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wr_request_ready <= 1'b1;
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else if (wr_request_valid)
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wr_request_ready <= 1'b0;
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else if (wr_response_eot)
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wr_request_ready <= 1'b1;
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end
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always @(posedge s_axis_aclk) begin
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if (wr_request_valid & wr_request_ready)
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wr_length <= wr_request_length[LENGTH_WIDTH-1:SRC_ADDR_ALIGN];
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end
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wire wr_last_beat;
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assign wr_last_beat = s_axis_valid & s_axis_ready & ((wr_addr == wr_length) | s_axis_last);
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always @(posedge s_axis_aclk) begin
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if (~wr_request_enable)
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s_axis_ready <= 1'b0;
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else if (wr_request_valid & wr_request_ready)
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s_axis_ready <= 1'b1;
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else if (wr_last_beat) begin
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s_axis_ready <= 1'b0;
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end
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end
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always @(posedge s_axis_aclk) begin
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if (s_axis_valid & s_axis_ready)
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wr_response_eot <= s_axis_last | (wr_addr == wr_length);
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else
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wr_response_eot <= 1'b0;
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end
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always @(posedge s_axis_aclk) begin
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if (wr_last_beat)
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wr_response_measured_length <= {wr_addr, {SRC_ADDR_ALIGN{1'b1}}};
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end
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reg wr_full = 1'b0;
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// Protect against larger transfers than storage
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always @(posedge s_axis_aclk) begin
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if (wr_request_valid & wr_request_ready)
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wr_full <= 1'b0;
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else if (&wr_addr & (s_axis_valid & s_axis_ready))
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wr_full <= 1'b1;
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end
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// Do not roll over write address
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always @(posedge s_axis_aclk) begin
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if (~wr_request_enable | wr_last_beat)
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wr_addr <= 'h0;
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else if (s_axis_valid & s_axis_ready & (~(&wr_addr)))
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wr_addr <= wr_addr + 1;
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end
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assign wr_enable = s_axis_valid & s_axis_ready & ~wr_full;
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
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.A_DATA_WIDTH (SRC_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DST_DATA_WIDTH)
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) i_mem (
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.clka (s_axis_aclk),
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.wea (wr_enable),
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.addra (wr_addr),
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.dina (s_axis_data),
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.clkb (m_axis_aclk),
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.reb (1'b1),
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.addrb (rd_addr),
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.doutb (rd_data)
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);
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reg rd_active = 1'b0;
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reg [1:0] rd_req_cnt = 2'b0;
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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rd_req_cnt <= rd_req_cnt + 2'b1;
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else if (rd_response_eot)
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rd_req_cnt <= rd_req_cnt - 2'b1;
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end
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assign rd_request_ready = ~rd_req_cnt[1];
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN];
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end
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assign rd_last_beat = (rd_addr == rd_length) & rd_enable;
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assign rd_response_eot = m_axis_last & m_axis_valid & m_axis_ready;
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// Read logic
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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rd_active <= 1'b1;
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else if (rd_last_beat)
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rd_active <= rd_req_cnt == 2;
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end
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assign rd_enable = rd_fifo_s_ready & rd_active &
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(rd_fifo_room >= (m_axis_valid&m_axis_ready ? 1 : RAM_LATENCY));
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always @(posedge m_axis_aclk) begin
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if (~rd_request_enable | rd_last_beat)
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rd_addr <= 'h0;
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else if (rd_enable)
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rd_addr <= rd_addr + 1;
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end
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// Delay read enable with latency cycles
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// <TODO> make this depend on parameter
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reg rd_valid_l1 = 1'b0;
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reg rd_valid_l2 = 1'b0;
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reg rd_last_l1 = 1'b0;
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reg rd_last_l2 = 1'b0;
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always @(posedge m_axis_aclk) begin
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rd_valid_l1 <= rd_enable;
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rd_last_l1 <= rd_last_beat;
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end
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// Extra pipeline to be sucked in by the BRAM/URAM output stage
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always @(posedge m_axis_aclk) begin
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if (rd_valid_l1)
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rd_data_l2 <= rd_data;
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end
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always @(posedge m_axis_aclk) begin
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if (rd_valid_l1)
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rd_valid_l2 <= 1'b1;
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else if (rd_fifo_s_ready)
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rd_valid_l2 <= 1'b0;
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if (rd_valid_l1)
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rd_last_l2 <= rd_last_l1;
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end
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assign rd_fifo_s_valid = rd_valid_l2;
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// Read datapath to AXIS logic
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util_axis_fifo #(
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.DATA_WIDTH(DST_DATA_WIDTH+1),
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.ADDRESS_WIDTH(2),
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.ASYNC_CLK(0),
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.M_AXIS_REGISTERED(0)
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) i_rd_fifo (
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.s_axis_aclk(m_axis_aclk),
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.s_axis_aresetn(m_axis_aresetn),
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.s_axis_valid(rd_fifo_s_valid),
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.s_axis_ready(rd_fifo_s_ready),
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.s_axis_full(),
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.s_axis_data({rd_last_l2,rd_data_l2}),
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.s_axis_room(rd_fifo_room),
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.s_axis_tkeep(),
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.s_axis_tlast(),
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.s_axis_almost_full(),
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.m_axis_aclk(m_axis_aclk),
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.m_axis_aresetn(m_axis_aresetn),
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.m_axis_valid(m_axis_valid),
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.m_axis_ready(m_axis_ready),
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.m_axis_data({m_axis_last,m_axis_data}),
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.m_axis_level(),
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.m_axis_empty(),
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.m_axis_tkeep(),
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.m_axis_tlast(),
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.m_axis_almost_empty()
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);
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endmodule
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