pluto_hdl_adi/library/axi_dac_interpolate/cic_interp.v

615 lines
19 KiB
Verilog

// -------------------------------------------------------------
//
// Module: cic_interp
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
// Generated on: 2016-07-05 11:08:04
// -------------------------------------------------------------
// -------------------------------------------------------------
// HDL Code Generation Options:
//
// OptimizeForHDL: on
// EDAScriptGeneration: off
// AddPipelineRegisters: on
// Name: cic_interp
// AddRatePort: on
// InputDataType: numerictype(1,31,30)
// TargetLanguage: Verilog
// TestBenchName: cicinterpfilt_copy_tb
// TestBenchStimulus: step ramp chirp noise
// GenerateHDLTestBench: off
// -------------------------------------------------------------
// HDL Implementation : Fully parallel
// -------------------------------------------------------------
// Filter Settings:
//
// Discrete-Time FIR Multirate Filter (real)
// -----------------------------------------
// Filter Structure : Cascaded Integrator-Comb Interpolator
// Interpolation Factor : 50000
// Differential Delay : 1
// Number of Sections : 6
// Stable : Yes
// Linear Phase : No
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module cic_interp
(
clk,
clk_enable,
reset,
filter_in,
rate,
load_rate,
filter_out,
ce_out
);
input clk;
input clk_enable;
input reset;
input signed [30:0] filter_in; //sfix31_En30
input [15:0] rate; //ufix16
input load_rate;
output signed [109:0] filter_out; //sfix110_En30
output ce_out;
////////////////////////////////////////////////////////////////
//Module Architecture: cic_interp
////////////////////////////////////////////////////////////////
// Local Functions
// Type Definitions
// Constants
parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30
// Signals
wire [15:0] rate_unsigned; // ufix16
reg [15:0] cur_count = 0; // ufix16
wire phase_0; // boolean
//
reg signed [30:0] input_register = 0; // sfix31_En30
// -- Section 1 Signals
wire signed [30:0] section_in1; // sfix31_En30
wire signed [31:0] section_cast1; // sfix32_En30
reg signed [31:0] diff1 = 0; // sfix32_En30
wire signed [31:0] section_out1; // sfix32_En30
wire signed [31:0] sub_cast; // sfix32_En30
wire signed [31:0] sub_cast_1; // sfix32_En30
wire signed [32:0] sub_temp; // sfix33_En30
reg signed [31:0] cic_pipeline1 = 0; // sfix32_En30
// -- Section 2 Signals
wire signed [31:0] section_in2; // sfix32_En30
wire signed [32:0] section_cast2; // sfix33_En30
reg signed [32:0] diff2 = 0; // sfix33_En30
wire signed [32:0] section_out2; // sfix33_En30
wire signed [32:0] sub_cast_2; // sfix33_En30
wire signed [32:0] sub_cast_3; // sfix33_En30
wire signed [33:0] sub_temp_1; // sfix34_En30
reg signed [32:0] cic_pipeline2 = 0; // sfix33_En30
// -- Section 3 Signals
wire signed [32:0] section_in3; // sfix33_En30
wire signed [33:0] section_cast3; // sfix34_En30
reg signed [33:0] diff3 = 0; // sfix34_En30
wire signed [33:0] section_out3; // sfix34_En30
wire signed [33:0] sub_cast_4; // sfix34_En30
wire signed [33:0] sub_cast_5; // sfix34_En30
wire signed [34:0] sub_temp_2; // sfix35_En30
reg signed [33:0] cic_pipeline3 = 0; // sfix34_En30
// -- Section 4 Signals
wire signed [33:0] section_in4; // sfix34_En30
wire signed [34:0] section_cast4; // sfix35_En30
reg signed [34:0] diff4 = 0; // sfix35_En30
wire signed [34:0] section_out4; // sfix35_En30
wire signed [34:0] sub_cast_6; // sfix35_En30
wire signed [34:0] sub_cast_7; // sfix35_En30
wire signed [35:0] sub_temp_3; // sfix36_En30
reg signed [34:0] cic_pipeline4 = 0; // sfix35_En30
// -- Section 5 Signals
wire signed [34:0] section_in5; // sfix35_En30
wire signed [35:0] section_cast5; // sfix36_En30
reg signed [35:0] diff5 = 0; // sfix36_En30
wire signed [35:0] section_out5; // sfix36_En30
wire signed [35:0] sub_cast_8; // sfix36_En30
wire signed [35:0] sub_cast_9; // sfix36_En30
wire signed [36:0] sub_temp_4; // sfix37_En30
reg signed [35:0] cic_pipeline5 = 0; // sfix36_En30
// -- Section 6 Signals
wire signed [35:0] section_in6; // sfix36_En30
reg signed [35:0] diff6 = 0; // sfix36_En30
wire signed [35:0] section_out6; // sfix36_En30
wire signed [35:0] sub_cast_10; // sfix36_En30
wire signed [35:0] sub_cast_11; // sfix36_En30
wire signed [36:0] sub_temp_5; // sfix37_En30
reg signed [35:0] cic_pipeline6 = 0; // sfix36_En30
wire signed [35:0] upsampling; // sfix36_En30
// -- Section 7 Signals
wire signed [35:0] section_in7; // sfix36_En30
wire signed [35:0] sum1; // sfix36_En30
reg signed [35:0] section_out7 = 0; // sfix36_En30
wire signed [35:0] add_cast; // sfix36_En30
wire signed [35:0] add_cast_1; // sfix36_En30
wire signed [36:0] add_temp; // sfix37_En30
// -- Section 8 Signals
wire signed [35:0] section_in8; // sfix36_En30
wire signed [50:0] section_cast8; // sfix51_En30
wire signed [50:0] sum2; // sfix51_En30
reg signed [50:0] section_out8 = 0; // sfix51_En30
wire signed [50:0] add_cast_2; // sfix51_En30
wire signed [50:0] add_cast_3; // sfix51_En30
wire signed [51:0] add_temp_1; // sfix52_En30
// -- Section 9 Signals
wire signed [50:0] section_in9; // sfix51_En30
wire signed [65:0] section_cast9; // sfix66_En30
wire signed [65:0] sum3; // sfix66_En30
reg signed [65:0] section_out9 = 0; // sfix66_En30
wire signed [65:0] add_cast_4; // sfix66_En30
wire signed [65:0] add_cast_5; // sfix66_En30
wire signed [66:0] add_temp_2; // sfix67_En30
// -- Section 10 Signals
wire signed [65:0] section_in10; // sfix66_En30
wire signed [79:0] section_cast10; // sfix80_En30
wire signed [79:0] sum4; // sfix80_En30
reg signed [79:0] section_out10 = 0; // sfix80_En30
wire signed [79:0] add_cast_6; // sfix80_En30
wire signed [79:0] add_cast_7; // sfix80_En30
wire signed [80:0] add_temp_3; // sfix81_En30
// -- Section 11 Signals
wire signed [79:0] section_in11; // sfix80_En30
wire signed [94:0] section_cast11; // sfix95_En30
wire signed [94:0] sum5; // sfix95_En30
reg signed [94:0] section_out11 = 0; // sfix95_En30
wire signed [94:0] add_cast_8; // sfix95_En30
wire signed [94:0] add_cast_9; // sfix95_En30
wire signed [95:0] add_temp_4; // sfix96_En30
// -- Section 12 Signals
wire signed [94:0] section_in12; // sfix95_En30
wire signed [109:0] section_cast12; // sfix110_En30
wire signed [109:0] sum6; // sfix110_En30
reg signed [109:0] section_out12 = 0; // sfix110_En30
wire signed [109:0] add_cast_10; // sfix110_En30
wire signed [109:0] add_cast_11; // sfix110_En30
wire signed [110:0] add_temp_5; // sfix111_En30
reg [6:0] bitgain = 0; // ufix7
wire signed [109:0] output_typeconvert; // sfix110_En30
wire signed [109:0] muxinput_14; // sfix110_En16
wire signed [109:0] muxinput_34; // sfix110_E4
wire signed [109:0] muxinput_54; // sfix110_E24
wire signed [109:0] muxinput_74; // sfix110_E44
wire signed [109:0] muxinput_94; // sfix110_E64
//
reg signed [109:0] output_register = 0; // sfix110_En30
// Block Statements
assign rate_unsigned = rate;
always @ (posedge clk or posedge reset)
begin: ce_output
if (reset == 1'b1) begin
cur_count <= 16'b0000000000000000;
end
else begin
if (clk_enable == 1'b1) begin
if (load_rate == 1'b1) begin
cur_count <= 16'b0000000000000001;
end
else if (cur_count == rate_unsigned - 1) begin
cur_count <= 16'b0000000000000000;
end
else begin
cur_count <= cur_count + 1;
end
end
end
end // ce_output
assign phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0;
// ------------------ Input Register ------------------
always @ (posedge clk or posedge reset)
begin: input_reg_process
if (reset == 1'b1) begin
input_register <= 0;
end
else begin
if (phase_0 == 1'b1) begin
input_register <= filter_in;
end
end
end // input_reg_process
// ------------------ Section # 1 : Comb ------------------
assign section_in1 = input_register;
assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1});
assign sub_cast = section_cast1;
assign sub_cast_1 = diff1;
assign sub_temp = sub_cast - sub_cast_1;
assign section_out1 = sub_temp[31:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section1
if (reset == 1'b1) begin
diff1 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff1 <= section_cast1;
end
end
end // comb_delay_section1
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section1
if (reset == 1'b1) begin
cic_pipeline1 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline1 <= section_out1;
end
end
end // cic_pipeline_process_section1
// ------------------ Section # 2 : Comb ------------------
assign section_in2 = cic_pipeline1;
assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2});
assign sub_cast_2 = section_cast2;
assign sub_cast_3 = diff2;
assign sub_temp_1 = sub_cast_2 - sub_cast_3;
assign section_out2 = sub_temp_1[32:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section2
if (reset == 1'b1) begin
diff2 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff2 <= section_cast2;
end
end
end // comb_delay_section2
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section2
if (reset == 1'b1) begin
cic_pipeline2 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline2 <= section_out2;
end
end
end // cic_pipeline_process_section2
// ------------------ Section # 3 : Comb ------------------
assign section_in3 = cic_pipeline2;
assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3});
assign sub_cast_4 = section_cast3;
assign sub_cast_5 = diff3;
assign sub_temp_2 = sub_cast_4 - sub_cast_5;
assign section_out3 = sub_temp_2[33:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section3
if (reset == 1'b1) begin
diff3 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff3 <= section_cast3;
end
end
end // comb_delay_section3
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section3
if (reset == 1'b1) begin
cic_pipeline3 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline3 <= section_out3;
end
end
end // cic_pipeline_process_section3
// ------------------ Section # 4 : Comb ------------------
assign section_in4 = cic_pipeline3;
assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4});
assign sub_cast_6 = section_cast4;
assign sub_cast_7 = diff4;
assign sub_temp_3 = sub_cast_6 - sub_cast_7;
assign section_out4 = sub_temp_3[34:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section4
if (reset == 1'b1) begin
diff4 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff4 <= section_cast4;
end
end
end // comb_delay_section4
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section4
if (reset == 1'b1) begin
cic_pipeline4 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline4 <= section_out4;
end
end
end // cic_pipeline_process_section4
// ------------------ Section # 5 : Comb ------------------
assign section_in5 = cic_pipeline4;
assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5});
assign sub_cast_8 = section_cast5;
assign sub_cast_9 = diff5;
assign sub_temp_4 = sub_cast_8 - sub_cast_9;
assign section_out5 = sub_temp_4[35:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section5
if (reset == 1'b1) begin
diff5 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff5 <= section_cast5;
end
end
end // comb_delay_section5
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section5
if (reset == 1'b1) begin
cic_pipeline5 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline5 <= section_out5;
end
end
end // cic_pipeline_process_section5
// ------------------ Section # 6 : Comb ------------------
assign section_in6 = cic_pipeline5;
assign sub_cast_10 = section_in6;
assign sub_cast_11 = diff6;
assign sub_temp_5 = sub_cast_10 - sub_cast_11;
assign section_out6 = sub_temp_5[35:0];
always @ (posedge clk or posedge reset)
begin: comb_delay_section6
if (reset == 1'b1) begin
diff6 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
diff6 <= section_in6;
end
end
end // comb_delay_section6
always @ (posedge clk or posedge reset)
begin: cic_pipeline_process_section6
if (reset == 1'b1) begin
cic_pipeline6 <= 0;
end
else begin
if (phase_0 == 1'b1) begin
cic_pipeline6 <= section_out6;
end
end
end // cic_pipeline_process_section6
assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 :
zeroconst;
// ------------------ Section # 7 : Integrator ------------------
assign section_in7 = upsampling;
assign add_cast = section_in7;
assign add_cast_1 = section_out7;
assign add_temp = add_cast + add_cast_1;
assign sum1 = add_temp[35:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section7
if (reset == 1'b1) begin
section_out7 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out7 <= sum1;
end
end
end // integrator_delay_section7
// ------------------ Section # 8 : Integrator ------------------
assign section_in8 = section_out7;
assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8});
assign add_cast_2 = section_cast8;
assign add_cast_3 = section_out8;
assign add_temp_1 = add_cast_2 + add_cast_3;
assign sum2 = add_temp_1[50:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section8
if (reset == 1'b1) begin
section_out8 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out8 <= sum2;
end
end
end // integrator_delay_section8
// ------------------ Section # 9 : Integrator ------------------
assign section_in9 = section_out8;
assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9});
assign add_cast_4 = section_cast9;
assign add_cast_5 = section_out9;
assign add_temp_2 = add_cast_4 + add_cast_5;
assign sum3 = add_temp_2[65:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section9
if (reset == 1'b1) begin
section_out9 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out9 <= sum3;
end
end
end // integrator_delay_section9
// ------------------ Section # 10 : Integrator ------------------
assign section_in10 = section_out9;
assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10});
assign add_cast_6 = section_cast10;
assign add_cast_7 = section_out10;
assign add_temp_3 = add_cast_6 + add_cast_7;
assign sum4 = add_temp_3[79:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section10
if (reset == 1'b1) begin
section_out10 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out10 <= sum4;
end
end
end // integrator_delay_section10
// ------------------ Section # 11 : Integrator ------------------
assign section_in11 = section_out10;
assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11});
assign add_cast_8 = section_cast11;
assign add_cast_9 = section_out11;
assign add_temp_4 = add_cast_8 + add_cast_9;
assign sum5 = add_temp_4[94:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section11
if (reset == 1'b1) begin
section_out11 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out11 <= sum5;
end
end
end // integrator_delay_section11
// ------------------ Section # 12 : Integrator ------------------
assign section_in12 = section_out11;
assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12});
assign add_cast_10 = section_cast12;
assign add_cast_11 = section_out12;
assign add_temp_5 = add_cast_10 + add_cast_11;
assign sum6 = add_temp_5[109:0];
always @ (posedge clk or posedge reset)
begin: integrator_delay_section12
if (reset == 1'b1) begin
section_out12 <= 0;
end
else begin
if (clk_enable == 1'b1) begin
section_out12 <= sum6;
end
end
end // integrator_delay_section12
always @(rate_unsigned)
begin
case(rate_unsigned)
16'b0000000000000101 : bitgain = 7'b0001110;
16'b0000000000110010 : bitgain = 7'b0100010;
16'b0000000111110100 : bitgain = 7'b0110110;
16'b0001001110001000 : bitgain = 7'b1001010;
16'b1100001101010000 : bitgain = 7'b1011110;
default : bitgain = 7'b1011110;
endcase
end
assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]});
assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]});
assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]});
assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]});
assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]});
assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
(bitgain == 7'b0100010) ? muxinput_34 :
(bitgain == 7'b0110110) ? muxinput_54 :
(bitgain == 7'b1001010) ? muxinput_74 :
muxinput_94;
// ------------------ Output Register ------------------
always @ (posedge clk or posedge reset)
begin: output_reg_process
if (reset == 1'b1) begin
output_register <= 0;
end
else begin
if (clk_enable == 1'b1) begin
output_register <= output_typeconvert;
end
end
end // output_reg_process
// Assignment Statements
assign ce_out = phase_0;
assign filter_out = output_register;
endmodule // cic_interp