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pluto_hdl_adi/library/axi_adrv9001
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Laszlo Nagy 6a4b46ebb4 axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 
If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 		2021-12-08 17:31:53 +02:00
..
intel axi_adrv9001/intel: Add dummy parameters to match Xilinx interface 2021-11-12 14:09:14 +02:00
Makefile Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
adrv9001_aligner4.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_aligner8.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_pack.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_rx.v axi_adrv9001: Add the option of global clock buffers on 7 series 2021-11-08 13:53:51 +02:00
adrv9001_rx_link.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
adrv9001_tx.v axi_adrv9001: Add the option of global clock buffers on 7 series 2021-11-08 13:53:51 +02:00
adrv9001_tx_link.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001.v axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 2021-12-08 17:31:53 +02:00
axi_adrv9001_constr.sdc axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
axi_adrv9001_constr.xdc axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
axi_adrv9001_core.v axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 2021-12-08 17:31:53 +02:00
axi_adrv9001_hw.tcl adrv9001[intel]: Add second pair of DMAs 2021-09-01 15:04:14 +03:00
axi_adrv9001_if.v axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 2021-12-08 17:31:53 +02:00
axi_adrv9001_ip.tcl axi_adrv9001: Add TDD support 2021-01-20 13:00:01 +02:00
axi_adrv9001_rx.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_rx_channel.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_tdd.v axi_adrv9001: Let gate signals have initial value, useful for simulation 2021-05-26 15:44:45 +03:00
axi_adrv9001_tx.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_tx_channel.v library:axi_adrv9001: Initial version 2020-08-24 17:49:12 +03:00