234 lines
6.8 KiB
Verilog
234 lines
6.8 KiB
Verilog
// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1)
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`timescale 1ns/100ps
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module axi_ad9963_if #(
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// this parameter controls the buffer type based on the target device.
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parameter DEVICE_TYPE = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive)
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input trx_clk,
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input trx_iq,
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input [11:0] trx_data,
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// physical interface (transmit)
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input tx_clk,
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output tx_iq,
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output [11:0] tx_data,
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// clock (common to both receive and transmit)
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input rst,
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output l_clk,
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output dac_clk,
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input dac_rst,
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// receive data path interface
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output reg adc_valid,
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output reg [23:0] adc_data,
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output reg adc_status,
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// transmit data path interface
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input dac_valid,
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input [23:0] dac_data,
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// delay interface
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input up_clk,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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reg [11:0] rx_data_p = 0;
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reg [11:0] tx_data_p = 'd0;
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reg [11:0] tx_data_n = 'd0;
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// internal signals
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wire [11:0] rx_data_p_s;
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wire [11:0] rx_data_n_s;
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wire rx_iq_p_s;
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wire rx_iq_n_s;
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wire tx_clk_serdes;
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wire div_clk;
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genvar l_inst;
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always @(posedge l_clk) begin
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if( rx_iq_p_s == 1'b1) begin
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adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I
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adc_valid <= 1'b1; // data[23:12] Q
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end else begin
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rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge
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adc_data <= {rx_data_p, rx_data_n_s} ; // so we take current N data with previous P data
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adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA
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end
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end
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always @(posedge dac_clk) begin
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if(dac_valid == 1'b1) begin
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tx_data_p <= dac_data[11:0] ;
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tx_data_n <= dac_data[23:12];
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end
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end
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always @(posedge l_clk) begin
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if (rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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// device clock interface (receive clock)
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BUFG i_clk_gbuf (
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.I (trx_clk),
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.O (l_clk));
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// receive data interface, ibuf -> idelay -> iddr
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_data (
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.rx_clk (l_clk),
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.rx_data_in_p (trx_data[l_inst]),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_data_p_s[l_inst]),
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.rx_data_n (rx_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[l_inst]),
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.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// receive iq interface, ibuf -> idelay -> iddr
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_iq (
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.rx_clk (l_clk),
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.rx_data_in_p (trx_iq),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_iq_p_s),
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.rx_data_n (rx_iq_n_s),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[12]),
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.up_dwdata (up_adc_dwdata[64:60]),
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.up_drdata (up_adc_drdata[64:60]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// transmit data interface
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BUFG dac_bufg (
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.I(div_clk),
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.O(dac_clk));
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ad_serdes_clk #(
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.DEVICE_TYPE(DEVICE_TYPE),
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.DDR_OR_SDR_N(0),
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.MMCM_OR_BUFR_N (1'b0),
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.CLKIN_DS_OR_SE_N(0),
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.SERDES_FACTOR(2))
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tx_serdes_clk (
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.rst(1'b0),
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.clk_in_p(tx_clk),
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.clk_in_n(1'b0),
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.clk(tx_clk_serdes),
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.div_clk(div_clk),
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.out_clk(),
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.loaden(),
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.phase(),
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.up_clk(1'b0),
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.up_rstn(1'b0),
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.up_drp_sel(1'b0),
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.up_drp_wr(1'b0),
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.up_drp_addr(12'h0),
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.up_drp_wdata(32'h0),
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.up_drp_rdata(),
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.up_drp_ready(),
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.up_drp_locked());
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ad_serdes_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.DDR_OR_SDR_N (1'b0),
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.SERDES_FACTOR(2),
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.DATA_WIDTH (13))
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i_serdes_out_data (
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.rst (dac_rst),
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.clk (tx_clk_serdes),
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.div_clk (div_clk),
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.loaden (1'b0),
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.data_s0 ({1'b1,tx_data_p}),
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.data_s1 ({1'b0,tx_data_n}),
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.data_s2 (13'h0),
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.data_s3 (13'h0),
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.data_s4 (13'h0),
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.data_s5 (13'h0),
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.data_s6 (13'h0),
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.data_s7 (13'h0),
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.data_out_se ({tx_iq,tx_data}),
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.data_out_p (),
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.data_out_n ());
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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