..
altera
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
xilinx
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
Makefile
Regenerate library Makefiles using the new shared Makefile include
2018-04-11 15:09:54 +03:00
axi_ad9361.v
a10soc: Connect AXI register reset
2018-04-11 15:09:54 +03:00
axi_ad9361_constr.sdc
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc
axi_ad9361: Update constraint file
2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl
axi_ad9361: Fix the last incorrect merge
2017-10-03 09:15:23 +01:00
axi_ad9361_ip.tcl
axi_*: Infer clock and reset signals of an IP
2018-04-11 15:09:54 +03:00
axi_ad9361_rx.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_rx_channel.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_rx_pnmon.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_tdd.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_tdd_if.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_tx.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
axi_ad9361_tx_channel.v
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00