606 lines
21 KiB
Verilog
606 lines
21 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module axi_dmac #(
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parameter ID = 0,
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_LENGTH_WIDTH = 24,
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parameter DMA_2D_TRANSFER = 0,
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parameter ASYNC_CLK_REQ_SRC = 1,
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parameter ASYNC_CLK_SRC_DEST = 1,
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parameter ASYNC_CLK_DEST_REQ = 1,
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parameter AXI_SLICE_DEST = 0,
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parameter AXI_SLICE_SRC = 0,
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parameter SYNC_TRANSFER_START = 0,
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parameter CYCLIC = 1,
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parameter DMA_AXI_PROTOCOL_DEST = 0,
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parameter DMA_AXI_PROTOCOL_SRC = 0,
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parameter DMA_TYPE_DEST = 0,
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parameter DMA_TYPE_SRC = 2,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter MAX_BYTES_PER_BURST = 128,
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parameter FIFO_SIZE = 8, // In bursts
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parameter AXI_ID_WIDTH_SRC = 4,
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parameter AXI_ID_WIDTH_DEST = 4,
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parameter DISABLE_DEBUG_REGISTERS = 0)(
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [11:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [11:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// Interrupt
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output irq,
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// Master AXI interface
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input m_dest_axi_aclk,
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input m_dest_axi_aresetn,
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// Write address
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output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_awaddr,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
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output [ 2:0] m_dest_axi_awsize,
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output [ 1:0] m_dest_axi_awburst,
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output [ 2:0] m_dest_axi_awprot,
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output [ 3:0] m_dest_axi_awcache,
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output m_dest_axi_awvalid,
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input m_dest_axi_awready,
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output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_awid,
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output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_awlock,
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// Write data
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output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
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output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
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input m_dest_axi_wready,
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output m_dest_axi_wvalid,
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output m_dest_axi_wlast,
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output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_wid,
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// Write response
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input m_dest_axi_bvalid,
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input [ 1:0] m_dest_axi_bresp,
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output m_dest_axi_bready,
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input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_bid,
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// Unused read interface
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output m_dest_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_araddr,
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output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
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output [ 2:0] m_dest_axi_arsize,
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output [ 1:0] m_dest_axi_arburst,
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output [ 3:0] m_dest_axi_arcache,
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output [ 2:0] m_dest_axi_arprot,
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input m_dest_axi_arready,
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input m_dest_axi_rvalid,
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input [ 1:0] m_dest_axi_rresp,
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input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
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output m_dest_axi_rready,
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output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_arid,
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output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_arlock,
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input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_rid,
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input m_dest_axi_rlast,
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// Master AXI interface
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input m_src_axi_aclk,
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input m_src_axi_aresetn,
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// Read address
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input m_src_axi_arready,
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output m_src_axi_arvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_araddr,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
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output [ 2:0] m_src_axi_arsize,
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output [ 1:0] m_src_axi_arburst,
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output [ 2:0] m_src_axi_arprot,
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output [ 3:0] m_src_axi_arcache,
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output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_arid,
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output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_arlock,
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// Read data and response
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input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
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output m_src_axi_rready,
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input m_src_axi_rvalid,
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input [ 1:0] m_src_axi_rresp,
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input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_rid,
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input m_src_axi_rlast,
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// Unused write interface
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output m_src_axi_awvalid,
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output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_awaddr,
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output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
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output [ 2:0] m_src_axi_awsize,
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output [ 1:0] m_src_axi_awburst,
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output [ 3:0] m_src_axi_awcache,
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output [ 2:0] m_src_axi_awprot,
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input m_src_axi_awready,
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output m_src_axi_wvalid,
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output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
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output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
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output m_src_axi_wlast,
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input m_src_axi_wready,
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input m_src_axi_bvalid,
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input [ 1:0] m_src_axi_bresp,
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output m_src_axi_bready,
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output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_awid,
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output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_awlock,
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output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid,
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input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid,
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// Slave streaming AXI interface
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input s_axis_aclk,
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output s_axis_ready,
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input s_axis_valid,
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input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
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input [0:0] s_axis_user,
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input s_axis_last,
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output s_axis_xfer_req,
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// Master streaming AXI interface
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input m_axis_aclk,
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input m_axis_ready,
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output m_axis_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
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output m_axis_last,
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output m_axis_xfer_req,
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// Input FIFO interface
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input fifo_wr_clk,
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input fifo_wr_en,
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input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
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output fifo_wr_overflow,
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input fifo_wr_sync,
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output fifo_wr_xfer_req,
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// Input FIFO interface
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input fifo_rd_clk,
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input fifo_rd_en,
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output fifo_rd_valid,
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output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
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output fifo_rd_underflow,
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output fifo_rd_xfer_req
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);
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localparam DMA_TYPE_AXI_MM = 0;
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localparam DMA_TYPE_AXI_STREAM = 1;
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localparam DMA_TYPE_FIFO = 2;
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localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
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localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
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// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
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localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
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DMA_DATA_WIDTH_DEST > 512 ? 7 :
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DMA_DATA_WIDTH_DEST > 256 ? 6 :
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DMA_DATA_WIDTH_DEST > 128 ? 5 :
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DMA_DATA_WIDTH_DEST > 64 ? 4 :
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DMA_DATA_WIDTH_DEST > 32 ? 3 :
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DMA_DATA_WIDTH_DEST > 16 ? 2 :
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DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
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localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
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DMA_DATA_WIDTH_SRC > 512 ? 7 :
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DMA_DATA_WIDTH_SRC > 256 ? 6 :
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DMA_DATA_WIDTH_SRC > 128 ? 5 :
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DMA_DATA_WIDTH_SRC > 64 ? 4 :
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DMA_DATA_WIDTH_SRC > 32 ? 3 :
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DMA_DATA_WIDTH_SRC > 16 ? 2 :
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DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
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localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 :
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(FIFO_SIZE) > 32 ? 7 :
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(FIFO_SIZE) > 16 ? 6 :
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(FIFO_SIZE) > 8 ? 5 :
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(FIFO_SIZE) > 4 ? 4 :
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(FIFO_SIZE) > 2 ? 3 :
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(FIFO_SIZE) > 1 ? 2 : 1;
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localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH;
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/* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of
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256 beats per burst. If either bus is AXI3 set the maximum number of beats
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per burst to 16. For non AXI interfaces the maximum beats per burst is in
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theory unlimted. Set it to 1024 to provide a reasonable upper threshold */
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localparam BEATS_PER_BURST_LIMIT_DEST =
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(DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ?
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(DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) :
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1024;
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localparam BYTES_PER_BURST_LIMIT_DEST =
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BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8;
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localparam BEATS_PER_BURST_LIMIT_SRC =
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(DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ?
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(DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) :
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1024;
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localparam BYTES_PER_BURST_LIMIT_SRC =
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BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8;
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/* The smaller bus limits the maximum bytes per burst. */
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localparam BYTES_PER_BURST_LIMIT =
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(BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ?
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BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC;
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/* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the
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interfaces can support. Limit the value if necessary. */
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localparam REAL_MAX_BYTES_PER_BURST =
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BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ?
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BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST;
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// ID signals from the DMAC, just for debugging
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wire [ID_WIDTH-1:0] dest_request_id;
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wire [ID_WIDTH-1:0] dest_data_id;
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wire [ID_WIDTH-1:0] dest_address_id;
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wire [ID_WIDTH-1:0] dest_response_id;
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wire [ID_WIDTH-1:0] src_request_id;
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wire [ID_WIDTH-1:0] src_data_id;
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wire [ID_WIDTH-1:0] src_address_id;
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wire [ID_WIDTH-1:0] src_response_id;
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wire [7:0] dbg_status;
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wire [31:0] dbg_ids0;
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wire [31:0] dbg_ids1;
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assign m_dest_axi_araddr = 'd0;
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assign m_dest_axi_arlen = 'd0;
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assign m_dest_axi_arsize = 'd0;
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assign m_dest_axi_arburst = 'd0;
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assign m_dest_axi_arcache = 'd0;
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assign m_dest_axi_arprot = 'd0;
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assign m_dest_axi_awid = 'h0;
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assign m_dest_axi_awlock = 'h0;
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assign m_dest_axi_wid = 'h0;
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assign m_dest_axi_arid = 'h0;
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assign m_dest_axi_arlock = 'h0;
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assign m_src_axi_awaddr = 'd0;
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assign m_src_axi_awlen = 'd0;
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assign m_src_axi_awsize = 'd0;
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assign m_src_axi_awburst = 'd0;
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assign m_src_axi_awcache = 'd0;
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assign m_src_axi_awprot = 'd0;
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assign m_src_axi_wdata = 'd0;
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assign m_src_axi_wstrb = 'd0;
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assign m_src_axi_wlast = 'd0;
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assign m_src_axi_awid = 'h0;
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assign m_src_axi_awlock = 'h0;
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assign m_src_axi_wid = 'h0;
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assign m_src_axi_arid = 'h0;
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assign m_src_axi_arlock = 'h0;
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wire dma_req_valid;
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wire dma_req_ready;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
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wire [DMA_LENGTH_WIDTH-1:0] dma_req_length;
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wire dma_req_eot;
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wire dma_req_sync_transfer_start;
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wire dma_req_last;
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wire up_req_eot;
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wire ctrl_enable;
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wire ctrl_pause;
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wire up_dma_req_valid;
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wire up_dma_req_ready;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address;
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wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address;
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wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length;
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wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length;
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wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride;
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wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride;
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wire up_dma_req_sync_transfer_start;
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wire up_dma_req_last;
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assign dbg_ids0 = {
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{DBG_ID_PADDING{1'b0}}, dest_response_id,
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{DBG_ID_PADDING{1'b0}}, dest_data_id,
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{DBG_ID_PADDING{1'b0}}, dest_address_id,
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{DBG_ID_PADDING{1'b0}}, dest_request_id
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};
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assign dbg_ids1 = {
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{DBG_ID_PADDING{1'b0}}, src_response_id,
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{DBG_ID_PADDING{1'b0}}, src_data_id,
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{DBG_ID_PADDING{1'b0}}, src_address_id,
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{DBG_ID_PADDING{1'b0}}, src_request_id
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};
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axi_dmac_regmap #(
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.DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS),
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.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
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.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
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.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
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.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
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.DMA_CYCLIC(CYCLIC),
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.HAS_DEST_ADDR(HAS_DEST_ADDR),
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.HAS_SRC_ADDR(HAS_SRC_ADDR),
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.DMA_2D_TRANSFER(DMA_2D_TRANSFER)
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) i_regmap (
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.s_axi_aclk(s_axi_aclk),
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.s_axi_aresetn(s_axi_aresetn),
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.s_axi_awvalid(s_axi_awvalid),
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.s_axi_awaddr(s_axi_awaddr),
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.s_axi_awready(s_axi_awready),
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.s_axi_awprot(s_axi_awprot),
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.s_axi_wvalid(s_axi_wvalid),
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.s_axi_wdata(s_axi_wdata),
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.s_axi_wstrb(s_axi_wstrb),
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.s_axi_wready(s_axi_wready),
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.s_axi_bvalid(s_axi_bvalid),
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.s_axi_bresp(s_axi_bresp),
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.s_axi_bready(s_axi_bready),
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.s_axi_arvalid(s_axi_arvalid),
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.s_axi_araddr(s_axi_araddr),
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.s_axi_arready(s_axi_arready),
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.s_axi_arprot(s_axi_arprot),
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.s_axi_rvalid(s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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.s_axi_rresp(s_axi_rresp),
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.s_axi_rdata(s_axi_rdata),
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// Interrupt
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.irq(irq),
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// Control interface
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.ctrl_enable(ctrl_enable),
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.ctrl_pause(ctrl_pause),
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// Request interface
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.request_valid(up_dma_req_valid),
|
|
.request_ready(up_dma_req_ready),
|
|
.request_dest_address(up_dma_req_dest_address),
|
|
.request_src_address(up_dma_req_src_address),
|
|
.request_x_length(up_dma_req_x_length),
|
|
.request_y_length(up_dma_req_y_length),
|
|
.request_dest_stride(up_dma_req_dest_stride),
|
|
.request_src_stride(up_dma_req_src_stride),
|
|
.request_sync_transfer_start(up_dma_req_sync_transfer_start),
|
|
.request_last(up_dma_req_last),
|
|
|
|
// DMA response interface
|
|
.response_eot(up_req_eot),
|
|
|
|
// Debug interface
|
|
.dbg_dest_addr(m_dest_axi_awaddr),
|
|
.dbg_src_addr(m_src_axi_araddr),
|
|
.dbg_status(dbg_status),
|
|
.dbg_ids0(dbg_ids0),
|
|
.dbg_ids1(dbg_ids1)
|
|
);
|
|
|
|
generate if (DMA_2D_TRANSFER == 1) begin
|
|
|
|
dmac_2d_transfer #(
|
|
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
|
|
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
|
|
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
|
|
) i_2d_transfer (
|
|
.req_aclk(s_axi_aclk),
|
|
.req_aresetn(s_axi_aresetn),
|
|
|
|
.req_eot(up_req_eot),
|
|
|
|
.req_valid(up_dma_req_valid),
|
|
.req_ready(up_dma_req_ready),
|
|
.req_dest_address(up_dma_req_dest_address),
|
|
.req_src_address(up_dma_req_src_address),
|
|
.req_x_length(up_dma_req_x_length),
|
|
.req_y_length(up_dma_req_y_length),
|
|
.req_dest_stride(up_dma_req_dest_stride),
|
|
.req_src_stride(up_dma_req_src_stride),
|
|
.req_sync_transfer_start(up_dma_req_sync_transfer_start),
|
|
|
|
.out_req_valid(dma_req_valid),
|
|
.out_req_ready(dma_req_ready),
|
|
.out_req_dest_address(dma_req_dest_address),
|
|
.out_req_src_address(dma_req_src_address),
|
|
.out_req_length(dma_req_length),
|
|
.out_req_sync_transfer_start(dma_req_sync_transfer_start),
|
|
.out_eot(dma_req_eot)
|
|
);
|
|
|
|
assign dma_req_last = 1'b0;
|
|
|
|
end else begin
|
|
|
|
assign dma_req_valid = up_dma_req_valid;
|
|
assign up_dma_req_ready = dma_req_ready;
|
|
assign dma_req_dest_address = up_dma_req_dest_address;
|
|
assign dma_req_src_address = up_dma_req_src_address;
|
|
assign dma_req_length = up_dma_req_x_length;
|
|
assign dma_req_sync_transfer_start = up_dma_req_sync_transfer_start;
|
|
assign dma_req_last = up_dma_req_last;
|
|
assign up_req_eot = dma_req_eot;
|
|
|
|
end endgenerate
|
|
|
|
dmac_request_arb #(
|
|
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
|
|
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
|
|
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
|
|
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
|
|
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
|
|
.DMA_TYPE_DEST(DMA_TYPE_DEST),
|
|
.DMA_TYPE_SRC(DMA_TYPE_SRC),
|
|
.DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
|
|
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
|
|
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
|
|
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
|
|
.AXI_SLICE_DEST(AXI_SLICE_DEST),
|
|
.AXI_SLICE_SRC(AXI_SLICE_SRC),
|
|
.MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST),
|
|
.FIFO_SIZE(FIFO_SIZE),
|
|
.ID_WIDTH(ID_WIDTH),
|
|
.AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)),
|
|
.AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST))
|
|
) i_request_arb (
|
|
.req_aclk(s_axi_aclk),
|
|
.req_aresetn(s_axi_aresetn),
|
|
|
|
.enable(ctrl_enable),
|
|
.pause(ctrl_pause),
|
|
|
|
.req_valid(dma_req_valid),
|
|
.req_ready(dma_req_ready),
|
|
.req_dest_address(dma_req_dest_address),
|
|
.req_src_address(dma_req_src_address),
|
|
.req_length(dma_req_length),
|
|
.req_xlast(dma_req_last),
|
|
.req_sync_transfer_start(dma_req_sync_transfer_start),
|
|
|
|
.eot(dma_req_eot),
|
|
|
|
.m_dest_axi_aclk(m_dest_axi_aclk),
|
|
.m_dest_axi_aresetn(m_dest_axi_aresetn),
|
|
.m_src_axi_aclk(m_src_axi_aclk),
|
|
.m_src_axi_aresetn(m_src_axi_aresetn),
|
|
|
|
.m_axi_awaddr(m_dest_axi_awaddr),
|
|
.m_axi_awlen(m_dest_axi_awlen),
|
|
.m_axi_awsize(m_dest_axi_awsize),
|
|
.m_axi_awburst(m_dest_axi_awburst),
|
|
.m_axi_awprot(m_dest_axi_awprot),
|
|
.m_axi_awcache(m_dest_axi_awcache),
|
|
.m_axi_awvalid(m_dest_axi_awvalid),
|
|
.m_axi_awready(m_dest_axi_awready),
|
|
|
|
.m_axi_wdata(m_dest_axi_wdata),
|
|
.m_axi_wstrb(m_dest_axi_wstrb),
|
|
.m_axi_wready(m_dest_axi_wready),
|
|
.m_axi_wvalid(m_dest_axi_wvalid),
|
|
.m_axi_wlast(m_dest_axi_wlast),
|
|
|
|
.m_axi_bvalid(m_dest_axi_bvalid),
|
|
.m_axi_bresp(m_dest_axi_bresp),
|
|
.m_axi_bready(m_dest_axi_bready),
|
|
|
|
.m_axi_arready(m_src_axi_arready),
|
|
.m_axi_arvalid(m_src_axi_arvalid),
|
|
.m_axi_araddr(m_src_axi_araddr),
|
|
.m_axi_arlen(m_src_axi_arlen),
|
|
.m_axi_arsize(m_src_axi_arsize),
|
|
.m_axi_arburst(m_src_axi_arburst),
|
|
.m_axi_arprot(m_src_axi_arprot),
|
|
.m_axi_arcache(m_src_axi_arcache),
|
|
|
|
.m_axi_rdata(m_src_axi_rdata),
|
|
.m_axi_rready(m_src_axi_rready),
|
|
.m_axi_rvalid(m_src_axi_rvalid),
|
|
.m_axi_rresp(m_src_axi_rresp),
|
|
|
|
.s_axis_aclk(s_axis_aclk),
|
|
.s_axis_ready(s_axis_ready),
|
|
.s_axis_valid(s_axis_valid),
|
|
.s_axis_data(s_axis_data),
|
|
.s_axis_user(s_axis_user),
|
|
.s_axis_last(s_axis_last),
|
|
.s_axis_xfer_req(s_axis_xfer_req),
|
|
|
|
.m_axis_aclk(m_axis_aclk),
|
|
.m_axis_ready(m_axis_ready),
|
|
.m_axis_valid(m_axis_valid),
|
|
.m_axis_data(m_axis_data),
|
|
.m_axis_last(m_axis_last),
|
|
.m_axis_xfer_req(m_axis_xfer_req),
|
|
|
|
.fifo_wr_clk(fifo_wr_clk),
|
|
.fifo_wr_en(fifo_wr_en),
|
|
.fifo_wr_din(fifo_wr_din),
|
|
.fifo_wr_overflow(fifo_wr_overflow),
|
|
.fifo_wr_sync(fifo_wr_sync),
|
|
.fifo_wr_xfer_req(fifo_wr_xfer_req),
|
|
|
|
.fifo_rd_clk(fifo_rd_clk),
|
|
.fifo_rd_en(fifo_rd_en),
|
|
.fifo_rd_valid(fifo_rd_valid),
|
|
.fifo_rd_dout(fifo_rd_dout),
|
|
.fifo_rd_underflow(fifo_rd_underflow),
|
|
.fifo_rd_xfer_req(fifo_rd_xfer_req),
|
|
|
|
// DBG
|
|
.dbg_dest_request_id(dest_request_id),
|
|
.dbg_dest_address_id(dest_address_id),
|
|
.dbg_dest_data_id(dest_data_id),
|
|
.dbg_dest_response_id(dest_response_id),
|
|
.dbg_src_request_id(src_request_id),
|
|
.dbg_src_address_id(src_address_id),
|
|
.dbg_src_data_id(src_data_id),
|
|
.dbg_src_response_id(src_response_id),
|
|
.dbg_status(dbg_status)
|
|
);
|
|
|
|
assign m_dest_axi_arvalid = 1'b0;
|
|
assign m_dest_axi_rready = 1'b0;
|
|
assign m_dest_axi_araddr = 'h0;
|
|
assign m_dest_axi_arlen = 'h0;
|
|
assign m_dest_axi_arsize = 'h0;
|
|
assign m_dest_axi_arburst = 'h0;
|
|
assign m_dest_axi_arcache = 'h0;
|
|
assign m_dest_axi_arprot = 'h0;
|
|
|
|
assign m_src_axi_awvalid = 1'b0;
|
|
assign m_src_axi_wvalid = 1'b0;
|
|
assign m_src_axi_bready = 1'b0;
|
|
assign m_src_axi_awvalid = 'h0;
|
|
assign m_src_axi_awaddr = 'h0;
|
|
assign m_src_axi_awlen = 'h0;
|
|
assign m_src_axi_awsize = 'h0;
|
|
assign m_src_axi_awburst = 'h0;
|
|
assign m_src_axi_awcache = 'h0;
|
|
assign m_src_axi_awprot = 'h0;
|
|
assign m_src_axi_wvalid = 'h0;
|
|
assign m_src_axi_wdata = 'h0;
|
|
assign m_src_axi_wstrb = 'h0;
|
|
assign m_src_axi_wlast = 'h0;
|
|
|
|
endmodule
|