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Lars-Peter Clausen 668b8bda62 util_axis_resize: Add support for specifying the endianness 
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2015-04-08 15:55:17 +02:00
library util_axis_resize: Add support for specifying the endianness 2015-04-08 15:55:17 +02:00
projects rfsom: Use interface connection for the I2S stream 2015-04-08 13:29:26 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md README: Update Vivado version number, 2014.4.1 is the new supported version 2015-03-03 09:48:13 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.4.1
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga