106 lines
3.7 KiB
Verilog
106 lines
3.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
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// clk_sel is 1. Provides a glitch free output clock
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// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_clkdiv (
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input clk,
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input clk_sel,
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output clk_out
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);
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parameter SIM_DEVICE = "7SERIES";
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parameter SEL_0_DIV = "4";
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parameter SEL_1_DIV = "2";
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wire clk_div_sel_0_s;
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wire clk_div_sel_1_s;
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generate if (SIM_DEVICE == "7SERIES") begin
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BUFR #(
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.BUFR_DIVIDE(SEL_0_DIV),
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.SIM_DEVICE("7SERIES")
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) clk_divide_sel_0 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_0_s));
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BUFR #(
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.BUFR_DIVIDE(SEL_1_DIV),
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.SIM_DEVICE("7SERIES")
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) clk_divide_sel_1 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_1_s));
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end else if (SIM_DEVICE == "ULTRASCALE") begin
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE(SEL_0_DIV)
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) clk_divide_sel_0 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_0_s));
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE(SEL_1_DIV)
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) clk_divide_sel_1 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_1_s));
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end endgenerate
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BUFGMUX_CTRL i_div_clk_gbuf (
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.I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
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.I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
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.S(clk_sel),
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.O (clk_out));
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endmodule // util_clkdiv
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