Lars-Peter Clausen c7989925c5 fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock ... Otherwise we get timing errors for the reset signal that is generated in the 50MHz clock domain, but used in the VGA PLL clock domain. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-09-09 15:05:06 +02:00
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system_bd.qsys	fmcomms2: c5soc: Set DMA transfer length to 24 bits	2014-09-09 15:05:06 +02:00
system_constr.sdc	fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock	2014-09-09 15:05:06 +02:00
system_project.tcl	fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.	2014-07-07 22:28:25 +03:00
system_timing.tcl	c5soc: initial a5soc copy	2014-07-01 13:09:38 -04:00
system_top.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00