Lars-Peter Clausen c7989925c5 fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock ... Otherwise we get timing errors for the reset signal that is generated in the 50MHz clock domain, but used in the VGA PLL clock domain. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2014-09-09 15:05:06 +02:00
..
ac701	FMCOMMS2 AC701 Project	2014-04-01 15:35:44 +03:00
c5soc	fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock	2014-09-09 15:05:06 +02:00
common	fmcomms2: Modified design to work with 4 channel util_adc_pack	2014-08-29 13:53:59 +03:00
kc705	FMCOMMS2 KC705 Project.	2014-03-24 11:48:52 +02:00
mitx045	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
ml605	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
vc707	FMCOMMS2 VC707 Project	2014-04-01 15:34:29 +03:00
zc702	Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project	2014-03-18 15:27:42 +02:00
zc706	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
zed	Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project	2014-03-18 15:27:42 +02:00