545 lines
15 KiB
Verilog
545 lines
15 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr4_act_n,
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ddr4_addr,
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ddr4_ba,
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ddr4_bg,
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ddr4_ck_p,
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ddr4_ck_n,
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ddr4_cke,
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ddr4_cs_n,
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ddr4_dm_n,
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ddr4_dq,
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ddr4_dqs_p,
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ddr4_dqs_n,
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ddr4_odt,
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ddr4_reset_n,
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mdio_mdc,
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mdio_mdio,
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phy_clk_p,
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phy_clk_n,
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phy_rst_n,
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phy_rx_p,
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phy_rx_n,
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phy_tx_p,
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phy_tx_n,
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fan_pwm,
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gpio_bd,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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rx_ref_clk_p,
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rx_ref_clk_n,
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rx_sysref_p,
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rx_sysref_n,
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rx_sync_p,
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rx_sync_n,
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rx_data_p,
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rx_data_n,
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tx_ref_clk_p,
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tx_ref_clk_n,
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tx_sysref_p,
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tx_sysref_n,
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tx_sync_p,
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tx_sync_n,
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tx_data_p,
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tx_data_n,
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trig_p,
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trig_n,
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adc_fdb,
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adc_fda,
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dac_irq,
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clkd_status,
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adc_pd,
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dac_txen,
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dac_reset,
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clkd_sync,
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spi_csn_clk,
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spi_csn_dac,
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spi_csn_adc,
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spi_clk,
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spi_sdio,
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spi_dir);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output ddr4_act_n;
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output [16:0] ddr4_addr;
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output [ 1:0] ddr4_ba;
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output [ 0:0] ddr4_bg;
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output ddr4_ck_p;
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output ddr4_ck_n;
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output [ 0:0] ddr4_cke;
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output [ 0:0] ddr4_cs_n;
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inout [ 7:0] ddr4_dm_n;
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inout [63:0] ddr4_dq;
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inout [ 7:0] ddr4_dqs_p;
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inout [ 7:0] ddr4_dqs_n;
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output [ 0:0] ddr4_odt;
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output ddr4_reset_n;
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output mdio_mdc;
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inout mdio_mdio;
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input phy_clk_p;
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input phy_clk_n;
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output phy_rst_n;
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input phy_rx_p;
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input phy_rx_n;
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output phy_tx_p;
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output phy_tx_n;
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output fan_pwm;
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inout [16:0] gpio_bd;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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input rx_ref_clk_p;
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input rx_ref_clk_n;
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input rx_sysref_p;
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input rx_sysref_n;
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output rx_sync_p;
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output rx_sync_n;
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input [ 3:0] rx_data_p;
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input [ 3:0] rx_data_n;
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input tx_ref_clk_p;
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input tx_ref_clk_n;
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input tx_sysref_p;
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input tx_sysref_n;
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input tx_sync_p;
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input tx_sync_n;
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output [ 3:0] tx_data_p;
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output [ 3:0] tx_data_n;
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input trig_p;
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input trig_n;
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inout adc_fdb;
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inout adc_fda;
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inout dac_irq;
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inout [ 1:0] clkd_status;
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inout adc_pd;
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inout dac_txen;
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inout dac_reset;
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inout clkd_sync;
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output spi_csn_clk;
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output spi_csn_dac;
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output spi_csn_adc;
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output spi_clk;
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inout spi_sdio;
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output spi_dir;
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// internal registers
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reg dac_drd = 'd0;
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reg [63:0] dac_ddata_0 = 'd0;
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reg [63:0] dac_ddata_1 = 'd0;
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reg [63:0] dac_ddata_2 = 'd0;
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reg [63:0] dac_ddata_3 = 'd0;
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reg adc_dsync = 'd0;
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reg adc_dwr = 'd0;
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reg [127:0] adc_ddata = 'd0;
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// internal signals
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wire [15:0] mb_intrs;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 7:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync;
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wire dac_clk;
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wire [127:0] dac_ddata;
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wire dac_enable_0;
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wire dac_enable_1;
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wire dac_enable_2;
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wire dac_enable_3;
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wire dac_valid_0;
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wire dac_valid_1;
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wire dac_valid_2;
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wire dac_valid_3;
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wire adc_clk;
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wire [63:0] adc_data_0;
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wire [63:0] adc_data_1;
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wire adc_enable_0;
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wire adc_enable_1;
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wire adc_valid_0;
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wire adc_valid_1;
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// adc-dac data
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always @(posedge dac_clk) begin
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case ({dac_enable_1, dac_enable_0})
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2'b11: begin
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dac_drd <= dac_valid_0 & dac_valid_1;
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dac_ddata_0[63:48] <= dac_ddata[111: 96];
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dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
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dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
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dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
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dac_ddata_1[63:48] <= dac_ddata[127:112];
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dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
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dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
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dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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end
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2'b10: begin
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dac_drd <= dac_valid_1 & ~dac_drd;
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dac_ddata_0 <= 64'd0;
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if (dac_drd == 1'b1) begin
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dac_ddata_1[63:48] <= dac_ddata[127:112];
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dac_ddata_1[47:32] <= dac_ddata[111: 96];
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dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
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dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
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end else begin
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dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
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dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
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dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
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dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
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end
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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end
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2'b01: begin
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dac_drd <= dac_valid_0 & ~dac_drd;
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if (dac_drd == 1'b1) begin
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dac_ddata_0[63:48] <= dac_ddata[127:112];
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dac_ddata_0[47:32] <= dac_ddata[111: 96];
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dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
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dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
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end else begin
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dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
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dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
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dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
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dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
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end
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dac_ddata_1 <= 64'd0;
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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end
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default: begin
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dac_drd <= 1'b0;
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dac_ddata_0 <= 64'd0;
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dac_ddata_1 <= 64'd0;
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dac_ddata_2 <= 64'd0;
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dac_ddata_3 <= 64'd0;
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end
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endcase
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end
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always @(posedge adc_clk) begin
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case ({adc_enable_1, adc_enable_0})
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2'b11: begin
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adc_dsync <= 1'b1;
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adc_dwr <= adc_valid_1 & adc_valid_0;
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adc_ddata[127:112] <= adc_data_1[63:48];
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adc_ddata[111: 96] <= adc_data_0[63:48];
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adc_ddata[ 95: 80] <= adc_data_1[47:32];
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adc_ddata[ 79: 64] <= adc_data_0[47:32];
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adc_ddata[ 63: 48] <= adc_data_1[31:16];
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adc_ddata[ 47: 32] <= adc_data_0[31:16];
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adc_ddata[ 31: 16] <= adc_data_1[15: 0];
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adc_ddata[ 15: 0] <= adc_data_0[15: 0];
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end
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2'b10: begin
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adc_dsync <= 1'b1;
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adc_dwr <= adc_valid_1 & ~adc_dwr;
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adc_ddata[127:112] <= adc_data_1[63:48];
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adc_ddata[111: 96] <= adc_data_1[47:32];
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adc_ddata[ 95: 80] <= adc_data_1[31:16];
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adc_ddata[ 79: 64] <= adc_data_1[15: 0];
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adc_ddata[ 63: 48] <= adc_ddata[127:112];
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adc_ddata[ 47: 32] <= adc_ddata[111: 96];
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adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
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adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
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end
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2'b01: begin
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adc_dsync <= 1'b1;
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adc_dwr <= adc_valid_0 & ~adc_dwr;
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adc_ddata[127:112] <= adc_data_0[63:48];
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adc_ddata[111: 96] <= adc_data_0[47:32];
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adc_ddata[ 95: 80] <= adc_data_0[31:16];
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adc_ddata[ 79: 64] <= adc_data_0[15: 0];
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adc_ddata[ 63: 48] <= adc_ddata[127:112];
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adc_ddata[ 47: 32] <= adc_ddata[111: 96];
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adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
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adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
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end
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default: begin
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adc_dsync <= 1'b0;
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adc_dwr <= 1'b0;
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adc_ddata <= 128'd0;
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end
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endcase
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end
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// spi
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assign spi_csn_adc = spi_csn[2];
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assign spi_csn_dac = spi_csn[1];
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assign spi_csn_clk = spi_csn[0];
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// default logic
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assign fan_pwm = 1'b1;
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// instantiations
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IBUFDS_GTE3 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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IBUFDS_GTE3 i_ibufds_tx_ref_clk (
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.CEB (1'd0),
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.I (tx_ref_clk_p),
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.IB (tx_ref_clk_n),
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.O (tx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_tx_sysref (
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.I (tx_sysref_p),
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.IB (tx_sysref_n),
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.O (tx_sysref));
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IBUFDS i_ibufds_tx_sync (
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.I (tx_sync_p),
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.IB (tx_sync_n),
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.O (tx_sync));
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daq2_spi i_spi (
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.spi_csn (spi_csn[2:0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (trig));
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assign gpio_i[43] = trig;
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ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
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.dt ({gpio_t[42:40], gpio_t[38], gpio_t[36:32]}),
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.di ({gpio_o[42:40], gpio_o[38], gpio_o[36:32]}),
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.do ({gpio_i[42:40], gpio_i[38], gpio_i[36:32]}),
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.dio ({ adc_pd, // 42
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dac_txen, // 41
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dac_reset, // 40
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clkd_sync, // 38
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adc_fdb, // 36
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adc_fda, // 35
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dac_irq, // 34
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clkd_status})); // 32
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
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.dt (gpio_t[16:0]),
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.di (gpio_o[16:0]),
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.do (gpio_i[16:0]),
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.dio (gpio_bd));
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system_wrapper i_system_wrapper (
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.adc_clk (adc_clk),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_ddata (adc_ddata),
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.adc_dsync (adc_dsync),
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.adc_dwr (adc_dwr),
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.adc_enable_0 (adc_enable_0),
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.adc_enable_1 (adc_enable_1),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.axi_ad9144_dma_intr (mb_intrs[13]),
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.axi_ad9680_dma_intr (mb_intrs[12]),
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.c0_ddr4_act_n (ddr4_act_n),
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.c0_ddr4_adr (ddr4_addr),
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.c0_ddr4_ba (ddr4_ba),
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.c0_ddr4_bg (ddr4_bg),
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.c0_ddr4_ck_c (ddr4_ck_n),
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.c0_ddr4_ck_t (ddr4_ck_p),
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.c0_ddr4_cke (ddr4_cke),
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.c0_ddr4_cs_n (ddr4_cs_n),
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.c0_ddr4_dm_n (ddr4_dm_n),
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.c0_ddr4_dq (ddr4_dq),
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.c0_ddr4_dqs_c (ddr4_dqs_n),
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|
.c0_ddr4_dqs_t (ddr4_dqs_p),
|
|
.c0_ddr4_odt (ddr4_odt),
|
|
.c0_ddr4_reset_n (ddr4_reset_n),
|
|
.dac_clk (dac_clk),
|
|
.dac_ddata (dac_ddata),
|
|
.dac_ddata_0 (dac_ddata_0),
|
|
.dac_ddata_1 (dac_ddata_1),
|
|
.dac_ddata_2 (dac_ddata_2),
|
|
.dac_ddata_3 (dac_ddata_3),
|
|
.dac_drd (dac_drd),
|
|
.dac_enable_0 (dac_enable_0),
|
|
.dac_enable_1 (dac_enable_1),
|
|
.dac_enable_2 (dac_enable_2),
|
|
.dac_enable_3 (dac_enable_3),
|
|
.dac_valid_0 (dac_valid_0),
|
|
.dac_valid_1 (dac_valid_1),
|
|
.dac_valid_2 (dac_valid_2),
|
|
.dac_valid_3 (dac_valid_3),
|
|
.gpio0_i (gpio_i[31:0]),
|
|
.gpio0_o (gpio_o[31:0]),
|
|
.gpio0_t (gpio_t[31:0]),
|
|
.gpio1_i (gpio_i[63:32]),
|
|
.gpio1_o (gpio_o[63:32]),
|
|
.gpio1_t (gpio_t[63:32]),
|
|
.hdmi_data (hdmi_data),
|
|
.hdmi_data_e (hdmi_data_e),
|
|
.hdmi_hsync (hdmi_hsync),
|
|
.hdmi_out_clk (hdmi_out_clk),
|
|
.hdmi_vsync (hdmi_vsync),
|
|
.iic_main_scl_io (iic_scl),
|
|
.iic_main_sda_io (iic_sda),
|
|
.mb_intr_05 (mb_intrs[5]),
|
|
.mb_intr_06 (mb_intrs[6]),
|
|
.mb_intr_12 (mb_intrs[12]),
|
|
.mb_intr_13 (mb_intrs[13]),
|
|
.mb_intr_14 (mb_intrs[14]),
|
|
.mb_intr_15 (mb_intrs[15]),
|
|
.mdio_mdc (mdio_mdc),
|
|
.mdio_mdio_io (mdio_mdio),
|
|
.phy_clk_clk_n (phy_clk_n),
|
|
.phy_clk_clk_p (phy_clk_p),
|
|
.phy_rst_n (phy_rst_n),
|
|
.phy_sd (1'b1),
|
|
.rx_data_n (rx_data_n),
|
|
.rx_data_p (rx_data_p),
|
|
.rx_ref_clk (rx_ref_clk),
|
|
.rx_sync (rx_sync),
|
|
.rx_sysref (rx_sysref),
|
|
.sgmii_rxn (phy_rx_n),
|
|
.sgmii_rxp (phy_rx_p),
|
|
.sgmii_txn (phy_tx_n),
|
|
.sgmii_txp (phy_tx_p),
|
|
.spdif (spdif),
|
|
.spi_clk_i (spi_clk),
|
|
.spi_clk_o (spi_clk),
|
|
.spi_csn_i (spi_csn),
|
|
.spi_csn_o (spi_csn),
|
|
.spi_sdi_i (spi_miso),
|
|
.spi_sdo_i (spi_mosi),
|
|
.spi_sdo_o (spi_mosi),
|
|
.sys_clk_clk_n (sys_clk_n),
|
|
.sys_clk_clk_p (sys_clk_p),
|
|
.sys_rst (sys_rst),
|
|
.tx_data_n (tx_data_n),
|
|
.tx_data_p (tx_data_p),
|
|
.tx_ref_clk (tx_ref_clk),
|
|
.tx_sync (tx_sync),
|
|
.tx_sysref (tx_sysref),
|
|
.uart_sin (uart_sin),
|
|
.uart_sout (uart_sout));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|