371 lines
12 KiB
Verilog
371 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_d,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// hps-gpio (max-v-u16)
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inout [ 3:0] hps_gpio,
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// gpio (max-v-u21)
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input [ 7:0] gpio_bd_i,
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output [ 3:0] gpio_bd_o,
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// lane interface
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input rx_ref_clk,
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input rx_device_clk,
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input rx_sysref,
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output rx_sync_0,
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output rx_sync_1,
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input [ 3:0] rx_data,
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input adc_fdb,
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input adc_fda,
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output adc_pdwn,
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// DAQ board's ADC SPI
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output spi_adc_csn,
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output spi_adc_clk,
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output spi_adc_mosi,
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input spi_adc_miso,
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// DAQ board's clock chip
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output spi_clkgen_csn,
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output spi_clkgen_clk,
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output spi_clkgen_mosi,
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input spi_clkgen_miso,
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// DAQ board's vco chip
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output spi_vco_csn,
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output spi_vco_clk,
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output spi_vco_mosi,
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// AFE board's DAC
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inout afe_dac_sda,
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inout afe_dac_scl,
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output afe_dac_clr_n,
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output afe_dac_load,
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// AFE board's ADC
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output afe_adc_sclk,
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output afe_adc_scn,
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input afe_adc_sdi,
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output afe_adc_convst,
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// Laser driver differential line
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output laser_driver,
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output laser_driver_en_n,
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input laser_driver_otw_n,
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// GPIO's for the laser board
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inout [13:0] laser_gpio,
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// Vref selects for AFE board
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output [ 7:0] tia_chsel
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);
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// internal signals
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wire [63:0] gpio_o;
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wire [63:0] gpio_i;
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wire sys_resetn_s;
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wire rx_sync_s;
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// assignments
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// gpio in & out are separate cores
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assign gpio_i[51:38] = gpio_o[51:38];
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assign afe_adc_convst = gpio_o[37];
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assign afe_dac_load = gpio_o[36];
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assign afe_dac_clr_n = gpio_o[35];
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assign adc_pdwn = gpio_o[34];
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assign gpio_i[33] = adc_fda;
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assign gpio_i[32] = adc_fdb;
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// board stuff (max-v-u21)
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assign gpio_i[31:12] = gpio_o[31:12];
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assign gpio_i[11: 4] = gpio_bd_i;
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assign gpio_i[ 3: 0] = gpio_o[ 3: 0];
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assign gpio_bd_o = gpio_o[3:0];
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assign rx_sync_0 = rx_sync_s;
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assign rx_sync_1 = rx_sync_s;
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// peripheral reset
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assign sys_resetn_s = sys_resetn & sys_hps_resetn;
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// instantiations
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wire adc_tia_chsel_en_s;
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wire [31:0] adc_data_tia_chsel_s;
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util_tia_chsel #(
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.DATA_WIDTH (32))
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i_util_tia_chsel (
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.clk (rx_device_clk),
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.adc_tia_chsel_en (laser_driver),
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.adc_data_tia_chsel (adc_data_tia_chsel_s),
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.tia_chsel (tia_chsel)
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);
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wire dma_sync_s;
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wire fifo_wr_en_s;
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util_axis_syncgen #(
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.ASYNC_SYNC (1))
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i_util_axis_syncgen (
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.s_axis_aclk (rx_device_clk),
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.s_axis_aresetn (1'b1),
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.s_axis_ready (1'b1),
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.s_axis_valid (fifo_wr_en_s),
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.ext_sync (laser_driver),
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.s_axis_sync (dma_sync_s));
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// IO Buffers for I2C
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wire i2c_0_scl_out;
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wire i2c_0_scl_in;
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wire i2c_0_sda_in;
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wire i2c_0_sda_oe;
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ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c_0_scl_out), .o(i2c_0_scl_in), .io(afe_dac_scl));
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ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c_0_sda_oe), .o(i2c_0_sda_in), .io(afe_dac_sda));
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// Block design instance
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
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.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
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.sys_hps_ddr_mem_a (hps_ddr_a),
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.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
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.sys_hps_ddr_mem_ba (hps_ddr_ba),
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.sys_hps_ddr_mem_bg (hps_ddr_bg),
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.sys_hps_ddr_mem_cke (hps_ddr_cke),
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.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
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.sys_hps_ddr_mem_odt (hps_ddr_odt),
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.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
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.sys_hps_ddr_mem_par (hps_ddr_par),
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.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
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.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
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.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
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.sys_hps_ddr_mem_dq (hps_ddr_dq),
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.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
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.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
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.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
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.sys_hps_ddr_rstn_reset_n (sys_resetn),
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.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
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.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
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.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
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.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
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.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
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.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
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.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
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.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
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.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
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.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
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.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
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.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
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.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
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.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
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.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
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.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
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.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
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.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
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.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
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.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
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.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
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.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
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.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
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.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
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.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
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.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
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.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
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.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
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.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
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.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
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.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
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.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
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.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
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.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
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.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
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.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
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.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
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.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
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.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
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.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
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.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
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.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
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.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
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.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
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.sys_hps_out_rstn_reset_n (sys_hps_resetn),
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.sys_hps_rstn_reset_n (sys_resetn),
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.sys_rstn_reset_n (sys_resetn_s),
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// AFE's DAC I2C interface
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.sys_hps_i2c_0_sda_i (i2c_0_sda_in),
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.sys_hps_i2c_0_sda_oe (i2c_0_sda_oe),
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.sys_hps_i2c_0_scl_out_clk (i2c_0_scl_out),
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.sys_hps_i2c_0_scl_in_clk (i2c_0_scl_in),
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// SPI interface for ADC (AD9694)
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.sys_spi_MISO (spi_adc_miso),
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.sys_spi_MOSI (spi_adc_mosi),
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.sys_spi_SCLK (spi_adc_clk),
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.sys_spi_SS_n (spi_adc_csn),
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// SPI interface for DAQ's clock chip
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.sys_spi_clockgen_MISO (spi_clkgen_miso),
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.sys_spi_clockgen_MOSI (spi_clkgen_mosi),
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.sys_spi_clockgen_SCLK (spi_clkgen_clk),
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.sys_spi_clockgen_SS_n (spi_clkgen_csn),
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// SPI interface for DAQ's VCO
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.sys_spi_vco_MISO (spi_vco_mosi),
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.sys_spi_vco_MOSI (spi_vco_mosi),
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.sys_spi_vco_SCLK (spi_vco_clk),
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.sys_spi_vco_SS_n (spi_vco_csn),
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// SPI interface for AFE's ADC chip
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.sys_spi_afe_adc_MISO (afe_adc_sdi),
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.sys_spi_afe_adc_MOSI (),
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.sys_spi_afe_adc_SCLK (afe_adc_sclk),
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.sys_spi_afe_adc_SS_n (afe_adc_scn),
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// JESD204B for AD9694
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.rx_data_rx_serial_data (rx_data),
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.rx_ref_clk_clk (rx_ref_clk),
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.rx_sync_export (rx_sync_s),
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.rx_sysref_export (rx_sysref),
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.rx_device_clk_clk(rx_device_clk),
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// laser driver related ports
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.laser_driver_driver_pulse (laser_driver),
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.laser_driver_en_n_driver_en_n (laser_driver_en_n),
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.laser_driver_otw_n_driver_otw_n (laser_driver_otw_n),
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.tia_chsel_tia_chsel (tia_chsel),
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.laser_gpio_export (laser_gpio),
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// Dummy ADC channel for TIA
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.adc_data_tia_chsel_data (adc_data_tia_chsel_s),
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.adc_data_tia_chsel_valid (1'b1),
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.adc_data_tia_chsel_enable (1'b1),
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// DMA synchronization
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.fifo_wr_en_out_valid (fifo_wr_en_s),
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.fifo_wr_en_in_valid (fifo_wr_en_s),
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.fifo_wr_sync_sync (dma_sync_s)
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);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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