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pluto_hdl_adi/library/axi_dmac
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Mathias Tausen 3857bdd16b axi_dmac: generalize version check 
In some cases, the Vivado version can contain other characters than just
numbers. One such example is after applying the patch of AR# 71948,
which makes `version -short` return something like `2018.3_AR71948`.

This patch changes the version check to ignore anything after the first
two components of the version.
 		2020-04-03 11:18:59 +03:00
..
bd axi_dmac: generalize version check 2020-04-03 11:18:59 +03:00
tb tb_base: Fix various test benches 2019-05-17 11:20:48 +03:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile all: Rename altera to intel 2019-06-29 06:53:51 +03:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v up_axi.v: fixed bus width definition 2019-08-06 13:45:54 +03:00
axi_dmac_burst_memory.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: fix timing constraints 2019-08-08 14:26:07 +03:00
axi_dmac_hw.tcl up_axi.v: fixed bus width definition 2019-08-06 13:45:54 +03:00
axi_dmac_ip.tcl axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle 2019-07-08 16:08:06 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v up_axi.v: fixed bus width definition 2019-08-06 13:45:54 +03:00
axi_dmac_regmap_request.v axi_dmac: clear measured transfer length when core disabled 2019-05-24 11:11:08 +03:00
axi_dmac_reset_manager.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_resize_dest.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_resize_src.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
axi_dmac_transfer.v axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v axi_dmac: patch xfer_request 2019-05-24 11:11:08 +03:00
dest_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: patch for partial 2D transfer support 2019-05-24 11:11:08 +03:00
request_generator.v whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00