pluto_hdl_adi/projects/adrv9001/zcu102
Laszlo Nagy 677c154134 adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
2021-03-04 11:13:10 +02:00
..
Makefile makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
cmos_constr.xdc adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings 2021-03-04 11:13:10 +02:00
lvds_constr.xdc adrv9001/zcu102: Update interface signal names based on direction 2020-08-28 13:23:00 +03:00
system_bd.tcl adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing 2021-01-26 15:22:41 +02:00
system_constr.xdc adrv9001/zcu102: Add debug header 2021-01-26 15:22:41 +02:00
system_project.tcl library: Move ad_iobuf to the common library, as it's not Xilinx specific 2020-11-02 16:13:35 +02:00
system_top.v adrv9001/zcu102: Add debug header 2021-01-26 15:22:41 +02:00