91 lines
3.1 KiB
Verilog
91 lines
3.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_aligner8 (
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input clk,
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input [7:0] idata,
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input ivalid,
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input [7:0] strobe,
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output reg [7:0] odata,
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output ovalid
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);
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reg [7:0] idata_d = 'b0;
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reg ivalid_d = 'b0;
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always @(posedge clk) begin
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if (ivalid) begin
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idata_d <= idata;
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end
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ivalid_d <= ivalid;
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end
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reg [2:0] phase = 'h0;
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always @(posedge clk) begin
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if (ivalid) begin
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if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin
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casex (strobe)
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'b1xxx_xxxx : phase <= 0;
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'b01xx_xxxx : phase <= 1;
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'b001x_xxxx : phase <= 2;
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'b0001_xxxx : phase <= 3;
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'b0000_1xxx : phase <= 4;
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'b0000_01xx : phase <= 5;
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'b0000_001x : phase <= 6;
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'b0000_0001 : phase <= 7;
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default : phase <= phase;
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endcase
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end
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end
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end
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always @(posedge clk) begin
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case (phase)
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0 : odata <= idata_d;
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1 : odata <= {idata_d[6:0],idata[7:7]};
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2 : odata <= {idata_d[5:0],idata[7:6]};
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3 : odata <= {idata_d[4:0],idata[7:5]};
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4 : odata <= {idata_d[3:0],idata[7:4]};
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5 : odata <= {idata_d[2:0],idata[7:3]};
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6 : odata <= {idata_d[1:0],idata[7:2]};
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7 : odata <= {idata_d[0:0],idata[7:1]};
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endcase
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end
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assign ovalid = ivalid_d;
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endmodule
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