AndreiGrozav 74ad0d1e46 library: Update ... Older Vivado versions where incorrectly inferring interfaces -axi_ad9361 -axi_ad9963 -axi_adc_decimate -axi_adc_trigger -axi_clkgen -axi_dac_interpolate -axi_hdmi_tx -axi_i2s_adi -axi_logic_analyzer -spi_engine		2017-11-15 17:08:45 +02:00
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bd	axi_clkgen: Propagate clock settings to output pins	2017-04-20 20:36:33 +02:00
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_clkgen.v	library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size	2017-08-01 15:21:25 +02:00
axi_clkgen_constr.xdc	library- drp moved to up clock	2015-06-01 13:39:26 -04:00
axi_clkgen_ip.tcl	library: Update	2017-11-15 17:08:45 +02:00