407 lines
12 KiB
Verilog
Executable File
407 lines
12 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_tx (
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// dac interface
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dac_clk,
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dac_valid,
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dac_lb_enb_i1,
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dac_pn_enb_i1,
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dac_data_i1,
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dac_lb_enb_q1,
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dac_pn_enb_q1,
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dac_data_q1,
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dac_lb_enb_i2,
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dac_pn_enb_i2,
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dac_data_i2,
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dac_lb_enb_q2,
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dac_pn_enb_q2,
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dac_data_q2,
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dac_r1_mode,
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// transmit master/slave
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dac_enable_in,
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dac_enable_out,
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// dma interface
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dac_drd,
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dac_ddata,
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dac_dovf,
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dac_dunf,
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// processor interface
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wdata,
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up_rdata,
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up_ack);
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// parameters
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parameter DP_DISABLE = 0;
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parameter PCORE_ID = 0;
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// dac interface
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input dac_clk;
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output dac_valid;
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output dac_lb_enb_i1;
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output dac_pn_enb_i1;
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output [11:0] dac_data_i1;
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output dac_lb_enb_q1;
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output dac_pn_enb_q1;
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output [11:0] dac_data_q1;
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output dac_lb_enb_i2;
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output dac_pn_enb_i2;
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output [11:0] dac_data_i2;
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output dac_lb_enb_q2;
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output dac_pn_enb_q2;
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output [11:0] dac_data_q2;
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output dac_r1_mode;
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// transmit master/slave
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input dac_enable_in;
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output dac_enable_out;
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// dma interface
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output dac_drd;
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input [63:0] dac_ddata;
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input dac_dovf;
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input dac_dunf;
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// processor interface
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input [31:0] up_wdata;
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output [31:0] up_rdata;
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output up_ack;
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// internal registers
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reg dac_enable = 'd0;
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reg [ 7:0] dac_rate_cnt = 'd0;
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reg dac_dds_enable = 'd0;
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reg dac_dds_data_enable = 'd0;
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reg dac_dds_data_enable_toggle = 'd0;
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reg dac_drd = 'd0;
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reg [63:0] dac_dma_data = 'd0;
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reg [15:0] dac_dma_data_0 = 'd0;
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reg [15:0] dac_dma_data_1 = 'd0;
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reg [15:0] dac_dma_data_2 = 'd0;
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reg [15:0] dac_dma_data_3 = 'd0;
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reg dac_valid = 'd0;
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reg [11:0] dac_data_i1 = 'd0;
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reg [11:0] dac_data_q1 = 'd0;
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reg [11:0] dac_data_i2 = 'd0;
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reg [11:0] dac_data_q2 = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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// internal clock and resets
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wire dac_rst;
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// internal signals
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wire dac_enable_s;
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wire dac_datafmt_s;
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wire [ 3:0] dac_datasel_s;
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wire [ 7:0] dac_datarate_s;
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wire [15:0] dac_dds_data_0_s;
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wire [15:0] dac_dds_data_1_s;
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wire [15:0] dac_dds_data_2_s;
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wire [15:0] dac_dds_data_3_s;
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wire [31:0] up_rdata_0_s;
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wire up_ack_0_s;
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wire [31:0] up_rdata_1_s;
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wire up_ack_1_s;
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wire [31:0] up_rdata_2_s;
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wire up_ack_2_s;
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wire [31:0] up_rdata_3_s;
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wire up_ack_3_s;
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wire [31:0] up_rdata_s;
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wire up_ack_s;
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// master/slave
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assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in;
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always @(posedge dac_clk) begin
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dac_enable <= dac_enable_s;
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end
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// dds rate counters, dds phases are updated using data enables
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always @(posedge dac_clk) begin
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if ((dac_enable_s == 1'b0) || (dac_rate_cnt == 8'd0)) begin
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dac_rate_cnt <= dac_datarate_s;
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end else begin
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dac_rate_cnt <= dac_rate_cnt - 1'b1;
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end
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dac_dds_enable <= dac_enable_s;
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if (dac_rate_cnt == 8'd0) begin
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dac_dds_data_enable <= 1'b1;
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end else begin
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dac_dds_data_enable <= 1'b0;
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end
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end
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// dma interface
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always @(posedge dac_clk) begin
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if (dac_dds_data_enable == 1'b1) begin
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dac_dds_data_enable_toggle <= ~dac_dds_data_enable_toggle;
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end
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if (dac_r1_mode == 1'b1) begin
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dac_drd <= dac_dds_data_enable & dac_dds_data_enable_toggle & dac_enable;
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end else begin
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dac_drd <= dac_dds_data_enable & dac_enable;
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end
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if (dac_drd == 1'b1) begin
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dac_dma_data <= dac_ddata;
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end
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if (dac_dds_data_enable == 1'b1) begin
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if (dac_r1_mode == 1'b0) begin
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dac_dma_data_0 <= dac_dma_data[15: 0];
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dac_dma_data_1 <= dac_dma_data[31:16];
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dac_dma_data_2 <= dac_dma_data[47:32];
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dac_dma_data_3 <= dac_dma_data[63:48];
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end else if (dac_dds_data_enable_toggle == 1'b1) begin
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dac_dma_data_0 <= dac_dma_data[47:32];
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dac_dma_data_1 <= dac_dma_data[63:48];
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dac_dma_data_2 <= 16'd0;
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dac_dma_data_3 <= 16'd0;
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end else begin
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dac_dma_data_0 <= dac_dma_data[15: 0];
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dac_dma_data_1 <= dac_dma_data[31:16];
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dac_dma_data_2 <= 16'd0;
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dac_dma_data_3 <= 16'd0;
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end
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end
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end
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// dac outputs
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always @(posedge dac_clk) begin
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dac_valid <= dac_dds_data_enable;
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if (dac_datasel_s[3:1] == 3'd1) begin
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dac_data_i1 <= dac_dma_data_0[15:4];
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dac_data_q1 <= dac_dma_data_1[15:4];
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dac_data_i2 <= dac_dma_data_2[15:4];
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dac_data_q2 <= dac_dma_data_3[15:4];
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end else begin
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dac_data_i1 <= dac_dds_data_0_s[15:4];
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dac_data_q1 <= dac_dds_data_1_s[15:4];
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dac_data_i2 <= dac_dds_data_2_s[15:4];
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dac_data_q2 <= dac_dds_data_3_s[15:4];
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_ack <= 'd0;
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end else begin
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up_rdata <= up_rdata_s |
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up_rdata_0_s |
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up_rdata_1_s |
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up_rdata_2_s |
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up_rdata_3_s;
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up_ack <= up_ack_s |
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up_ack_0_s |
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up_ack_1_s |
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up_ack_2_s |
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up_ack_3_s;
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end
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end
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// dac channel
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axi_ad9361_tx_channel #(
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.CHID(0),
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.DP_DISABLE (DP_DISABLE))
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i_tx_channel_0 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_data (dac_dds_data_0_s),
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.dac_dds_enable (dac_dds_enable),
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.dac_dds_data_enable (dac_dds_data_enable),
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.dac_dds_format (dac_datafmt_s),
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.dac_dds_pattenb (dac_datasel_s[0]),
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.dac_lb_enb (dac_lb_enb_i1),
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.dac_pn_enb (dac_pn_enb_i1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_0_s),
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.up_ack (up_ack_0_s));
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// dac channel
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axi_ad9361_tx_channel #(
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.CHID(1),
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.DP_DISABLE (DP_DISABLE))
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i_tx_channel_1 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_data (dac_dds_data_1_s),
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.dac_dds_enable (dac_dds_enable),
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.dac_dds_data_enable (dac_dds_data_enable),
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.dac_dds_format (dac_datafmt_s),
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.dac_dds_pattenb (dac_datasel_s[0]),
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.dac_lb_enb (dac_lb_enb_q1),
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.dac_pn_enb (dac_pn_enb_q1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_1_s),
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.up_ack (up_ack_1_s));
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// dac channel
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axi_ad9361_tx_channel #(
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.CHID(2),
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.DP_DISABLE (DP_DISABLE))
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i_tx_channel_2 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_data (dac_dds_data_2_s),
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.dac_dds_enable (dac_dds_enable),
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.dac_dds_data_enable (dac_dds_data_enable),
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.dac_dds_format (dac_datafmt_s),
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.dac_dds_pattenb (dac_datasel_s[0]),
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.dac_lb_enb (dac_lb_enb_i2),
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.dac_pn_enb (dac_pn_enb_i2),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_2_s),
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.up_ack (up_ack_2_s));
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// dac channel
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axi_ad9361_tx_channel #(
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.CHID(3),
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.DP_DISABLE (DP_DISABLE))
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i_tx_channel_3 (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_dds_data (dac_dds_data_3_s),
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.dac_dds_enable (dac_dds_enable),
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.dac_dds_data_enable (dac_dds_data_enable),
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.dac_dds_format (dac_datafmt_s),
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.dac_dds_pattenb (dac_datasel_s[0]),
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.dac_lb_enb (dac_lb_enb_q2),
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.dac_pn_enb (dac_pn_enb_q2),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_3_s),
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.up_ack (up_ack_3_s));
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// dac common processor interface
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up_dac_common #(.PCORE_ID (PCORE_ID)) i_up_dac_common (
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.mmcm_rst (),
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_enable (dac_enable_out),
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.dac_frame (),
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.dac_par_type (),
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.dac_par_enb (),
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.dac_r1_mode (dac_r1_mode),
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.dac_datafmt (dac_datafmt_s),
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.dac_datasel (dac_datasel_s),
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.dac_datarate (dac_datarate_s),
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.dac_status (1'b1),
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.dac_status_ovf (dac_dovf),
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.dac_status_unf (dac_dunf),
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.dac_clk_ratio (32'd1),
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.drp_clk (1'b0),
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.drp_rst (),
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.drp_sel (),
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.drp_wr (),
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.drp_addr (),
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.drp_wdata (),
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.drp_rdata (16'd0),
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.drp_ready (1'd0),
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.drp_locked (1'd1),
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.up_usr_chanmax (),
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.dac_usr_chanmax (8'd3),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_s),
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.up_ack (up_ack_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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