219 lines
7.5 KiB
Verilog
Executable File
219 lines
7.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9250_alt (
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_data,
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// dma interface
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adc_clk,
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adc_dwr,
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adc_ddata,
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adc_dsync,
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adc_dovf,
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adc_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awid,
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s_axi_awlen,
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s_axi_awsize,
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s_axi_awburst,
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s_axi_awlock,
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s_axi_awcache,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wlast,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bid,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arid,
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s_axi_arlen,
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s_axi_arsize,
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s_axi_arburst,
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s_axi_arlock,
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s_axi_arcache,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rid,
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s_axi_rlast,
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s_axi_rready,
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// debug signals
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adc_mon_valid,
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adc_mon_data);
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parameter PCORE_ID = 0;
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parameter PCORE_AXI_ID_WIDTH = 3;
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parameter PCORE_DEVICE_TYPE = 0;
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk;
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input [63:0] rx_data;
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// dma interface
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output adc_clk;
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output adc_dwr;
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output [63:0] adc_ddata;
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output adc_dsync;
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input adc_dovf;
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input adc_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [13:0] s_axi_awaddr;
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input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
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input [ 7:0] s_axi_awlen;
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input [ 2:0] s_axi_awsize;
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input [ 1:0] s_axi_awburst;
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input [ 0:0] s_axi_awlock;
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input [ 3:0] s_axi_awcache;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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input s_axi_wlast;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [13:0] s_axi_araddr;
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input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
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input [ 7:0] s_axi_arlen;
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input [ 2:0] s_axi_arsize;
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input [ 1:0] s_axi_arburst;
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input [ 0:0] s_axi_arlock;
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input [ 3:0] s_axi_arcache;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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// debug signals
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output adc_mon_valid;
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output [119:0] adc_mon_data;
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// defaults
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assign s_axi_bid = 'd0;
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assign s_axi_rid = 'd0;
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assign s_axi_rlast = 1'd0;
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// ad9250 lite version
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axi_ad9250 #(
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.PCORE_ID (PCORE_ID),
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.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
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.PCORE_IODELAY_GROUP ("adc_if_delay_group"),
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.C_S_AXI_MIN_SIZE (32'hffff),
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.C_BASEADDR (32'h00000000),
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.C_HIGHADDR (32'hffffffff))
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i_ad9250 (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.adc_clk (adc_clk),
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.adc_dwr (adc_dwr),
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.adc_ddata (adc_ddata),
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.adc_dsync (adc_dsync),
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.adc_dovf (adc_dovf),
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.adc_dunf (adc_dunf),
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awaddr ({18'd0, s_axi_awaddr}),
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.s_axi_awready (s_axi_awready),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wready (s_axi_wready),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bready (s_axi_bready),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_araddr ({18'd0, s_axi_araddr}),
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.s_axi_arready (s_axi_arready),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rready (s_axi_rready),
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.adc_mon_valid (adc_mon_valid),
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.adc_mon_data (adc_mon_data));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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