43 lines
2.0 KiB
Tcl
43 lines
2.0 KiB
Tcl
# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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set dac_fifo_address_width 14
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/dac_fmc_ebz_bd.tcl
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ad_ip_parameter dac_jesd204_link/tx CONFIG.SYSREF_IOB false
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