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Lars-Peter Clausen c6c45fe1d5 adi_jesd204: Configure fPLL phase aligned mode 
In phase aligned mode the fPLL uses an external feedback path to better
align the phase of the PLL output to the phase of the external reference
clock.

This mode is required for deterministic latency to be able to sample SYSREF
which is source synchronous to the external reference clock signal.

So far phase aligned mode had been disabled since manual PLL calibration
would fail in this mode under certain (unknown) circumstances and dynamic
reconfiguration of the PLL would not work.

The latest Intel Arria 10 transceiver datasheet contains instructions for
the proper calibration sequence to make it work when the PLL is configured
for phase aligned mode. Software has been updated accordingly, so enable
phase aligned mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2020-12-14 13:59:11 +02:00
..
axi_ad5766 up_axi_update: ADDRESS_WIDTH parameter is now a localparam 2019-07-26 11:58:58 +03:00
axi_ad6676 axi_ad6676: Set data format to twos complement 2020-10-13 12:55:17 +03:00
axi_ad7616 axi_ad7616: Update ad_edge_detect port names 2020-10-28 11:31:50 +02:00
axi_ad9122 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9144 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9152 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9162 Fix copy-paste typo in *_ip.tcl 2019-07-29 15:37:30 +03:00
axi_ad9250 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9265 library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_ad9361 axi_ad9361: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
axi_ad9371 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9434 Fix copy-paste typo in *_ip.tcl 2019-07-29 15:37:30 +03:00
axi_ad9467 axi_ad9467: Fix missing connection warnings 2020-09-11 10:24:22 +03:00
axi_ad9625 Fix copy-paste typo in *_ip.tcl 2019-07-29 15:37:30 +03:00
axi_ad9671 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9680 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9684 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_ad9739a ad_serdes_out: Add tristate option 2020-08-07 08:31:19 +03:00
axi_ad9963 axi_ad9963: Add last sample hold support 2020-11-02 15:50:12 +02:00
axi_adc_decimate axi_adc_decimate: Export signals indicating the rate 2020-08-13 07:01:19 +03:00
axi_adc_trigger axi_adc_trigger: Use valid in data delay stage 2020-08-13 07:01:19 +03:00
axi_adrv9001 makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
axi_adrv9009 quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
axi_clkgen library/axi_clkgen: Fix second clock output 2020-01-07 13:21:00 +02:00
axi_dac_interpolate axi_dac_interpolate: Add last sample support 2020-11-02 15:50:12 +02:00
axi_dmac axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
axi_fan_control axi_fan_control: Fixed reset bug 2020-05-08 17:07:57 +03:00
axi_fmcadc5_sync library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_generic_adc axi_generic_adc: Declare parameters before use 2020-08-31 15:58:35 +03:00
axi_gpreg makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
axi_hdmi_rx library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_hdmi_tx axi_hdmi_tx: Remove deprecated constraint 2020-12-08 14:38:04 +02:00
axi_i2s_adi axi_i2s_adi: create friendly xgui files 2020-08-25 09:55:31 +03:00
axi_intr_monitor library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_laser_driver axi_laser_driver: Fix IP paramtere editor error 2020-08-11 10:14:18 +03:00
axi_logic_analyzer axi_logic_analyzer: Fix data width warning 2020-09-11 10:23:26 +03:00
axi_mc_controller library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_mc_current_monitor library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_mc_speed library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_pulse_gen axi_laser_driver: Add support for Intel platforms 2019-10-02 15:32:17 +03:00
axi_rd_wr_combiner library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_spdif_rx library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_spdif_tx library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
axi_sysid makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
axi_usb_fx3 library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
cn0363 library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
common ad_mux: another fix cases where channel number is not power of mux size 2020-11-27 09:45:11 +02:00
cordic_demod library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
intel adi_jesd204: Configure fPLL phase aligned mode 2020-12-14 13:59:11 +02:00
interfaces library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
jesd204 ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data) 2020-11-27 09:45:11 +02:00
scripts Add 'SE Base' family to the supported FPGAs 2020-09-15 18:14:23 +03:00
spi_engine spi_engine: Update util_axis_fifo instances 2020-12-04 11:00:53 +02:00
sysid_rom makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
util_adcfifo util_adcfifo: Update the interfaces for the asymetric memory 2020-08-11 10:14:18 +03:00
util_axis_fifo util_axis_fifo: Refactoring 2020-12-04 11:00:53 +02:00
util_axis_resize library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_axis_upscale library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_bsplit quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
util_cdc library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_cic library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_dacfifo Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
util_dec256sinc24b library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_delay library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_extract util_extract: Use less delays in axi_adc_trigger 2019-08-22 18:06:10 +03:00
util_fir_dec library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_fir_int library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_gmii_to_rgmii library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_i2c_mixer library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_mfifo library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_pack util_cpack2: support for 64 channels 2020-08-11 10:37:59 +03:00
util_pulse_gen library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_rfifo scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
util_sigma_delta_spi util_sigma_delta_spi: Fix syntax 2020-10-19 10:45:36 +03:00
util_tdd_sync library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_var_fifo library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
util_wfifo quartus_pro: Parameter property TYPE is not supported 2020-08-11 10:14:18 +03:00
xilinx library: Move ad_iobuf to the common library, as it's not Xilinx specific 2020-11-02 16:13:35 +02:00
Makefile library:axi_adrv9001: Initial version 2020-08-24 17:49:12 +03:00