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pluto_hdl_adi/library/axi_dmac
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Istvan Csomortani 06bab87733 axi_dmac: Reset fifo_rd_data when DMA is off - v2 
The first attempt (f3daf0) faild miserably. When the data_req signal
from the device had more than 1 cycle of deassert state, because of the
added latency of the data stream, the device got 'zeros' too.
In this fix, the DMA will hold the valid data on the bus, between two
consecutive data request. The bus is reseted just after all the data
were sent out.
 		2017-10-10 08:10:24 +01:00
..
bd axi_dmac: post_propagate(): Handle mappings with multiple address segments 2017-04-19 13:47:02 +02:00
2d_transfer.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
Makefile Create CDC helper library 2017-05-23 11:16:07 +02:00
address_generator.v axi_dmac: Fix some data width mismatches 2017-08-01 15:22:29 +02:00
axi_dmac.v axi_dmac: Better support debug IDs when ID_WIDTH != 3 2017-08-24 17:42:20 +02:00
axi_dmac_constr.sdc axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them 2015-07-23 17:01:02 +03:00
axi_dmac_constr.ttcl axi_dmac: Make debug register optional 2017-04-18 12:17:39 +02:00
axi_dmac_hw.tcl axi_dmac: Control s_axis_user/fifo_wr_sync validity 2017-10-03 09:32:14 +01:00
axi_dmac_ip.tcl Create CDC helper library 2017-05-23 11:16:07 +02:00
axi_register_slice.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
data_mover.v axi_dmac: Fix some data width mismatches 2017-08-01 15:22:29 +02:00
dest_axi_mm.v axi_dmac: dest_axi_mm: Use fixed wstrb signal 2017-08-01 15:22:29 +02:00
dest_axi_stream.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
dest_fifo_inf.v axi_dmac: Reset fifo_rd_data when DMA is off - v2 2017-10-10 08:10:24 +01:00
inc_id.h axi_dmac: Fix some data width mismatches 2017-08-01 15:22:29 +02:00
request_arb.v axi_dmac: dest_axi_mm: Use fixed wstrb signal 2017-08-01 15:22:29 +02:00
request_generator.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
resp.h Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00
response_generator.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
response_handler.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
splitter.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00
src_axi_mm.v axi_dmac: Comment out unused src_response interface 2017-08-01 15:22:29 +02:00
src_axi_stream.v axi_dmac: src_axi_stream: Terminate data mover m_axi_last signal 2017-08-01 15:22:29 +02:00
src_fifo_inf.v axi_dmac: Update to verilog-2001 coding style 2017-07-15 09:25:14 +01:00