AndreiGrozav 0cc5130c9a adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V		2017-03-01 11:32:17 +02:00
..
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
system_constr.sdc	adrv9371x: Updated constraints for altera projects	2016-11-04 18:20:46 +02:00
system_project.tcl	adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V	2017-03-01 11:32:17 +02:00
system_qsys.tcl	projects/altera* - default & common qsys commands	2016-12-20 16:27:44 -05:00
system_top.v	adrv9371_a10soc: Fixed port assignments	2017-03-01 11:32:17 +02:00