1d4b92190a
In Verilog-2001 standard, redeclaration of an output port as a wire is not allowed. |
||
|---|---|---|
| .. | ||
| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||
1d4b92190a
In Verilog-2001 standard, redeclaration of an output port as a wire is not allowed. |
||
|---|---|---|
| .. | ||
| Makefile | ||
| system_bd.tcl | ||
| system_constr.xdc | ||
| system_project.tcl | ||
| system_top.v | ||