Adrian Costina 8ed301a264 AC701: Common, removed system clock constraint		2015-04-02 11:51:20 +03:00
..
a5gt	a5gt:common: Added phy reset signal from ethernet in pin assignments	2015-01-23 12:31:41 +02:00
a5gte	a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2	2015-01-23 12:30:16 +02:00
a5soc	a5soc: fmcjesdadc1+hdmi version	2014-08-14 09:05:38 -04:00
ac701	AC701: Common, removed system clock constraint	2015-04-02 11:51:20 +03:00
c5soc	projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.	2014-08-27 21:46:23 +03:00
kc705	kc705/vc707: consistency fixes	2015-03-26 14:00:50 -04:00
kcu105	kcu105/adv7511: moved hdmi/spdif out of base design	2015-03-10 16:15:15 -04:00
mitx045	mitx: common, fixed number of gpios enabled	2015-03-31 16:16:40 +03:00
rfsom	rfsom: sd1 to sd0 changes	2015-03-19 09:34:14 -04:00
vc707	kc705/vc707: consistency fixes	2015-03-26 14:00:58 -04:00
xilinx	sys_dmafifo: ad_connect updates	2015-03-09 16:06:06 -04:00
zc702	zc702: Updated base design to the latest model	2015-03-13 12:44:08 +02:00
zc706	zc706_base: The FCLK_CLK2 is not used.	2015-03-11 18:10:32 +02:00
zed	fmcomms2_zed: Update design to the new hdl framework	2015-03-13 18:52:57 +02:00