36 lines
1.3 KiB
Makefile
36 lines
1.3 KiB
Makefile
####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_spi_engine
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GENERIC_DEPS += ../../common/ad_rst.v
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += axi_spi_engine.v
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XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += axi_spi_engine_constr.ttcl
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XILINX_DEPS += axi_spi_engine_ip.tcl
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
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XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
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XILINX_LIB_DEPS += util_axis_fifo
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XILINX_LIB_DEPS += util_cdc
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INTEL_DEPS += ../../common/ad_mem.v
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INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../../util_axis_fifo/address_gray.v
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INTEL_DEPS += ../../util_axis_fifo/address_gray_pipelined.v
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INTEL_DEPS += ../../util_axis_fifo/address_sync.v
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INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_gray.v
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INTEL_DEPS += axi_spi_engine_constr.sdc
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INTEL_DEPS += axi_spi_engine_hw.tcl
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include ../../scripts/library.mk
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