5aa11feb48
According to the documentation when using a BRAM block in SDP mode the REGCEB pin is not used and should be connected to GND. The tools though when inferring a BRAM connect REGCEB to the same signal REGCEA. This causes issues with timing verification since the REGCEB pin is associated with the write clock whereas the REGCEA pin is associated with the read clock. Until this is fixed in the tools mark all paths to the REGCEB pin as false paths. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.