553 lines
16 KiB
Verilog
Executable File
553 lines
16 KiB
Verilog
Executable File
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_tx #(
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter NUM_OUTPUT_PIPELINE = 0,
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
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parameter DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4,
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parameter TPL_DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4,
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parameter ENABLE_CHAR_REPLACE = 1'b0,
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parameter ASYNC_CLK = 1
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) (
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input clk,
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input reset,
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input device_clk,
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input device_reset,
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output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data,
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output [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk,
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output [2*NUM_LANES-1:0] phy_header,
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input sysref,
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output lmfc_edge,
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output lmfc_clk,
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input [NUM_LINKS-1:0] sync,
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input [TPL_DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_data,
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output tx_ready,
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output [TPL_DATA_PATH_WIDTH-1:0] tx_eof,
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output [TPL_DATA_PATH_WIDTH-1:0] tx_sof,
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output [TPL_DATA_PATH_WIDTH-1:0] tx_somf,
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output [TPL_DATA_PATH_WIDTH-1:0] tx_eomf,
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input tx_valid,
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input [NUM_LANES-1:0] cfg_lanes_disable,
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input [NUM_LINKS-1:0] cfg_links_disable,
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input [9:0] cfg_octets_per_multiframe,
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input [7:0] cfg_octets_per_frame,
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input cfg_continuous_cgs,
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input cfg_continuous_ilas,
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input cfg_skip_ilas,
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input [7:0] cfg_mframes_per_ilas,
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input cfg_disable_char_replacement,
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input cfg_disable_scrambler,
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input [9:0] device_cfg_octets_per_multiframe,
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input [7:0] device_cfg_octets_per_frame,
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input [7:0] device_cfg_beats_per_multiframe,
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input [7:0] device_cfg_lmfc_offset,
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input device_cfg_sysref_oneshot,
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input device_cfg_sysref_disable,
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output ilas_config_rd,
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output [1:0] ilas_config_addr,
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input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data,
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input ctrl_manual_sync_request,
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output device_event_sysref_edge,
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output device_event_sysref_alignment_error,
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output [NUM_LINKS-1:0] status_sync,
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output [1:0] status_state,
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output [31:0] status_synth_params0,
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output [31:0] status_synth_params1,
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output [31:0] status_synth_params2
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);
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localparam MAX_OCTETS_PER_FRAME = 32;
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localparam MAX_OCTETS_PER_MULTIFRAME =
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(MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
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localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
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localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1;
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localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
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MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
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MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
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MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
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MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
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MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
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MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
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MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
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localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
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localparam CW = DATA_PATH_WIDTH * NUM_LANES;
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localparam HW = 2 * NUM_LANES;
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wire [DW-1:0] phy_data_r;
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wire [CW-1:0] phy_charisk_r;
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wire [HW-1:0] phy_header_r;
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wire eof_gen_reset;
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wire tx_ready_64b_next;
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reg tx_ready_64b;
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wire frame_mark_reset;
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wire [DATA_PATH_WIDTH-1:0] tx_sof_fm;
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wire [DATA_PATH_WIDTH-1:0] tx_eof_fm;
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wire [DATA_PATH_WIDTH-1:0] tx_somf_fm;
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wire [DATA_PATH_WIDTH-1:0] tx_eomf_fm;
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reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d1;
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reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d1;
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reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d1;
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reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d1;
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reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d2;
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reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d2;
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reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d2;
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reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d2;
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wire lmfc_edge_synced;
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wire lmc_edge;
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wire lmc_quarter_edge;
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wire eoemb;
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wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] gearbox_data;
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wire tx_ready_nx;
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wire link_lmfc_edge;
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wire link_lmfc_clk;
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wire device_lmfc_edge;
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wire device_lmfc_clk;
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wire device_lmc_edge;
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wire device_lmc_quarter_edge;
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wire device_eoemb;
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wire tx_next_mf_ready;
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wire link_tx_ready;
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wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2;
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wire [7:0] device_cfg_beats_per_multiframe_s;
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// If input and output widths are symmetric keep the calculation for backwards
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// compatibility of the software.
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assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ?
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device_cfg_octets_per_multiframe >> DPW_LOG2 :
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device_cfg_beats_per_multiframe;
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jesd204_lmfc #(
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.LINK_MODE(LINK_MODE),
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.DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
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) i_lmfc (
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.clk(device_clk),
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.reset(device_reset),
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.cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
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.cfg_lmfc_offset(device_cfg_lmfc_offset),
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.cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
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.cfg_sysref_oneshot(device_cfg_sysref_oneshot),
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.cfg_sysref_disable(device_cfg_sysref_disable),
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.sysref(sysref),
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.sysref_edge(device_event_sysref_edge),
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.sysref_alignment_error(device_event_sysref_alignment_error),
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.lmfc_edge(device_lmfc_edge),
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.lmfc_clk(device_lmfc_clk),
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.lmfc_counter(),
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.lmc_edge(device_lmc_edge),
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.lmc_quarter_edge(device_lmc_quarter_edge),
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.eoemb(device_eoemb)
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);
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generate
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if (ASYNC_CLK) begin : dual_lmfc_mode
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reg link_lmfc_reset = 1'b1;
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reg device_lmfc_edge_d1 = 1'b0;
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reg device_tx_ready = 1'b0;
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jesd204_lmfc #(
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.LINK_MODE(LINK_MODE),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_link_lmfc (
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.clk(clk),
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.reset(link_lmfc_reset),
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.cfg_octets_per_multiframe(cfg_octets_per_multiframe),
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.cfg_lmfc_offset('h0),
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.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
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.cfg_sysref_oneshot(1'b0),
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.cfg_sysref_disable(1'b1),
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.sysref(sysref),
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.sysref_edge(),
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.sysref_alignment_error(),
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.lmfc_edge(link_lmfc_edge),
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.lmfc_clk(link_lmfc_clk),
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.lmfc_counter(),
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.lmc_edge(lmc_edge),
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.lmc_quarter_edge(lmc_quarter_edge),
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.eoemb(eoemb)
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);
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK(ASYNC_CLK)
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) i_link_reset_done_cdc (
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.in_bits(~reset),
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.out_clk(device_clk),
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.out_resetn(~device_reset),
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.out_bits(link_reset_n)
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);
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sync_event #(
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.NUM_OF_EVENTS (1)
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) i_sync_lmfc (
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.in_clk(device_clk),
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.in_event(device_lmfc_edge & link_reset_n),
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.out_clk(clk),
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.out_event(lmfc_edge_synced)
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);
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always @(posedge clk) begin
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if (reset) begin
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link_lmfc_reset <= 1'b1;
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end else if (lmfc_edge_synced) begin
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link_lmfc_reset <= 1'b0;
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end
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end
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jesd204_tx_gearbox #(
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.IN_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH),
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.OUT_DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.NUM_LANES(NUM_LANES),
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.DEPTH(8)
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) i_tx_gearbox(
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.link_clk(clk),
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.reset(reset),
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.device_clk(device_clk),
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.device_reset(device_reset),
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.device_data(tx_data),
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.device_lmfc_edge(device_lmfc_edge_d1),
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.link_data(gearbox_data),
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.output_ready(tx_ready_nx)
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);
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always @(posedge device_clk) begin
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device_lmfc_edge_d1 <= device_lmfc_edge;
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end
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK(ASYNC_CLK)
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) i_next_mf_ready_cdc (
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.in_bits(tx_next_mf_ready),
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.out_clk(device_clk),
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.out_resetn(1'b1),
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.out_bits(device_tx_next_mf_ready)
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);
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always @(posedge device_clk) begin
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if (device_reset) begin
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device_tx_ready <= 1'b0;
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end else if (device_lmfc_edge & device_tx_next_mf_ready) begin
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device_tx_ready <= 1'b1;
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end
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end
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jesd204_frame_mark #(
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.DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH)
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) i_device_frame_mark (
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.clk(device_clk),
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.reset(~device_tx_ready),
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.cfg_octets_per_multiframe(device_cfg_octets_per_multiframe),
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.cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s),
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.cfg_octets_per_frame(device_cfg_octets_per_frame),
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.sof(tx_sof),
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.eof(tx_eof),
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.somf(tx_somf),
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.eomf(tx_eomf)
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);
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assign tx_ready = device_tx_ready;
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end else begin
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assign link_lmfc_edge = device_lmfc_edge;
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assign link_lmfc_clk = device_lmfc_clk;
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assign lmc_edge = device_lmc_edge;
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assign lmc_quarter_edge = device_lmc_quarter_edge;
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assign eoemb = device_eoemb;
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assign gearbox_data = tx_data;
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assign tx_sof = (LINK_MODE == 1) ? tx_sof_fm_d2 : tx_sof_fm;
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assign tx_eof = (LINK_MODE == 1) ? tx_eof_fm_d2 : tx_eof_fm;
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assign tx_somf = (LINK_MODE == 1) ? tx_somf_fm_d2 : tx_somf_fm;
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assign tx_eomf = (LINK_MODE == 1) ? tx_eomf_fm_d2 : tx_eomf_fm;
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assign tx_ready = link_tx_ready;
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end
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endgenerate
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assign lmfc_edge = device_lmfc_edge;
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assign lmfc_clk = device_lmfc_clk;
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assign frame_mark_reset = (LINK_MODE == 1) ? eof_gen_reset : ~tx_ready_64b_next;
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jesd204_frame_mark #(
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.DATA_PATH_WIDTH (DATA_PATH_WIDTH)
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) i_frame_mark (
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.clk (clk),
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.reset (frame_mark_reset),
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.cfg_octets_per_multiframe (cfg_octets_per_multiframe),
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.cfg_beats_per_multiframe (cfg_beats_per_multiframe),
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.cfg_octets_per_frame (cfg_octets_per_frame),
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.sof (tx_sof_fm),
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.eof (tx_eof_fm),
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.somf (tx_somf_fm),
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.eomf (tx_eomf_fm)
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);
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always @(posedge clk) begin
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tx_sof_fm_d1 <= tx_sof_fm;
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tx_eof_fm_d1 <= tx_eof_fm;
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tx_somf_fm_d1 <= tx_somf_fm;
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tx_eomf_fm_d1 <= tx_eomf_fm;
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tx_sof_fm_d2 <= tx_sof_fm_d1;
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tx_eof_fm_d2 <= tx_eof_fm_d1;
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tx_somf_fm_d2 <= tx_somf_fm_d1;
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tx_eomf_fm_d2 <= tx_eomf_fm_d1;
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end
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generate
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genvar i;
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if (LINK_MODE[0] == 1) begin : mode_8b10b
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reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d3;
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reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d3;
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wire [NUM_LANES-1:0] lane_cgs_enable;
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wire [DW-1:0] ilas_data;
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wire [DATA_PATH_WIDTH*NUM_LANES-1:0] ilas_charisk;
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wire cfg_generate_eomf = 1'b1;
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always @(posedge clk) begin
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tx_eof_fm_d3 <= tx_eof_fm_d2;
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tx_eomf_fm_d3 <= tx_eomf_fm_d2;
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end
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jesd204_tx_ctrl #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_tx_ctrl (
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.clk(clk),
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.reset(reset),
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.sync(sync),
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.lmfc_edge(link_lmfc_edge),
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.somf(tx_somf_fm_d2),
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.somf_early2(tx_somf_fm),
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.eomf(tx_eomf_fm_d2),
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.lane_cgs_enable(lane_cgs_enable),
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.eof_reset(eof_gen_reset),
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.tx_ready(link_tx_ready),
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.tx_ready_nx(tx_ready_nx),
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.tx_next_mf_ready(tx_next_mf_ready),
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.ilas_data(ilas_data),
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.ilas_charisk(ilas_charisk),
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.ilas_config_addr(ilas_config_addr),
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.ilas_config_rd(ilas_config_rd),
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.ilas_config_data(ilas_config_data),
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.cfg_lanes_disable(cfg_lanes_disable),
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.cfg_links_disable(cfg_links_disable),
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.cfg_continuous_cgs(cfg_continuous_cgs),
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.cfg_continuous_ilas(cfg_continuous_ilas),
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.cfg_skip_ilas(cfg_skip_ilas),
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.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
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.cfg_octets_per_multiframe(cfg_octets_per_multiframe),
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.ctrl_manual_sync_request(ctrl_manual_sync_request),
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.status_sync(status_sync),
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.status_state(status_state)
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);
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for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
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localparam D_START = i * DATA_PATH_WIDTH*8;
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localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
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localparam C_START = i * DATA_PATH_WIDTH;
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localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
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jesd204_tx_lane #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE)
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) i_lane (
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.clk(clk),
|
|
|
|
.eof(tx_eof_fm_d3),
|
|
.eomf(tx_eomf_fm_d3),
|
|
|
|
.cgs_enable(lane_cgs_enable[i]),
|
|
|
|
.ilas_data(ilas_data[D_STOP:D_START]),
|
|
.ilas_charisk(ilas_charisk[C_STOP:C_START]),
|
|
|
|
.tx_data(gearbox_data[D_STOP:D_START]),
|
|
.tx_ready(link_tx_ready),
|
|
|
|
.phy_data(phy_data_r[D_STOP:D_START]),
|
|
.phy_charisk(phy_charisk_r[C_STOP:C_START]),
|
|
|
|
.cfg_octets_per_frame(cfg_octets_per_frame),
|
|
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
|
.cfg_disable_scrambler(cfg_disable_scrambler)
|
|
);
|
|
end
|
|
|
|
assign phy_header_r = 'h0;
|
|
|
|
end
|
|
|
|
if (LINK_MODE[1] == 1) begin : mode_64b66b
|
|
|
|
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
|
|
localparam D_START = i * DATA_PATH_WIDTH*8;
|
|
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
|
|
localparam H_START = i * 2;
|
|
localparam H_STOP = H_START + 2 -1;
|
|
jesd204_tx_lane_64b i_lane(
|
|
.clk(clk),
|
|
.reset(reset),
|
|
|
|
.tx_data(gearbox_data[D_STOP:D_START]),
|
|
.tx_ready(tx_ready_64b),
|
|
|
|
.phy_data(phy_data_r[D_STOP:D_START]),
|
|
.phy_header(phy_header_r[H_STOP:H_START]),
|
|
|
|
.lmc_edge(lmc_edge),
|
|
.lmc_quarter_edge(lmc_quarter_edge),
|
|
.eoemb(eoemb),
|
|
|
|
.cfg_disable_scrambler(cfg_disable_scrambler),
|
|
.cfg_header_mode(2'b0),
|
|
.cfg_lane_disable(cfg_lanes_disable[i])
|
|
);
|
|
end
|
|
|
|
assign tx_ready_64b_next = reset ? 1'b0 : (link_lmfc_edge || tx_ready_64b);
|
|
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
tx_ready_64b <= 1'b0;
|
|
end else begin
|
|
tx_ready_64b <= tx_ready_64b_next;
|
|
end
|
|
end
|
|
|
|
assign tx_ready_nx = tx_ready_64b_next;
|
|
assign tx_next_mf_ready = 1'b1;
|
|
|
|
assign link_tx_ready = tx_ready_64b;
|
|
// Link considered in DATA phase when SYSREF received and LEMC clock started
|
|
// running
|
|
assign status_state = {2{tx_ready_64b}};
|
|
|
|
|
|
assign phy_charisk_r = 'h0;
|
|
assign ilas_config_rd = 'h0;
|
|
assign ilas_config_addr = 'h0;
|
|
assign status_sync = 'h0;
|
|
|
|
end
|
|
|
|
endgenerate
|
|
|
|
pipeline_stage #(
|
|
.WIDTH(CW + DW + HW),
|
|
.REGISTERED(NUM_OUTPUT_PIPELINE)
|
|
) i_output_pipeline_stage (
|
|
.clk(clk),
|
|
.in({
|
|
phy_data_r,
|
|
phy_charisk_r,
|
|
phy_header_r
|
|
}),
|
|
.out({
|
|
phy_data,
|
|
phy_charisk,
|
|
phy_header
|
|
})
|
|
);
|
|
|
|
// Core static parameters
|
|
assign status_synth_params0 = {NUM_LANES};
|
|
assign status_synth_params1 = {
|
|
/*31:16 */ 16'b0,
|
|
/*15: 8 */ 3'b0,TPL_DATA_PATH_WIDTH[4:0],
|
|
/* 7: 0 */ 4'b0,DPW_LOG2[3:0]};
|
|
assign status_synth_params2 = {
|
|
/*31:16 */ 16'b0,
|
|
/*15:13 */ 3'b0,
|
|
/* 12 */ ASYNC_CLK[0],
|
|
/*11:10 */ 2'b0,
|
|
/* 9: 8 */ LINK_MODE[1:0],
|
|
/* 7: 0 */ NUM_LINKS[7:0]};
|
|
|
|
endmodule
|