Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers ... Make synthesis parameters accessible for the drivers. Rework implementation to reflect the parameters of the actual core and not of the AXI interfacing core.		2021-02-05 15:24:15 +02:00
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bd	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
Makefile	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_tx.v	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
jesd204_tx_constr.sdc	jesd204: Add Altera/Intel IP support	2017-08-21 11:09:42 +02:00
jesd204_tx_constr.ttcl	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_tx_ctrl.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_tx_gearbox.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_tx_header.v	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00
jesd204_tx_hw.tcl	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
jesd204_tx_ip.tcl	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
jesd204_tx_lane.v	jesd204: Make character replacement opt in feature	2021-02-05 15:24:15 +02:00
jesd204_tx_lane_64b.v	jesd204_tx: Support for 64b mode in transmit peripheral	2020-02-10 09:47:07 +02:00