413 lines
16 KiB
Verilog
413 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns / 1ps
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module data_offload #(
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parameter ID = 0,
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parameter [ 0:0] MEM_TYPE = 1'b0, // 1'b0 -FPGA RAM; 1'b1 - external memory
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parameter [33:0] MEM_SIZE = 1023, // memory size in bytes -1 - max 16 GB
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parameter MEMC_UIF_DATA_WIDTH = 512,
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parameter MEMC_UIF_ADDRESS_WIDTH = 31,
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parameter [31:0] MEMC_BADDRESS = 32'h00000000,
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parameter TX_OR_RXN_PATH = 0, // if set IP is used in TX path, other wise in RX path
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parameter SRC_DATA_WIDTH = 64,
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parameter SRC_RAW_DATA_EN = 1'b0,
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parameter SRC_ADDR_WIDTH = 8,
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parameter DST_ADDR_WIDTH = 7,
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parameter DST_DATA_WIDTH = 128,
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parameter DST_RAW_DATA_EN = 1'b0, // TBD
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parameter DST_CYCLIC_EN = 1'b0, // 1'b1 - CYCLIC mode enabled; 1'b0 - CYCLIC mode disabled
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parameter AUTO_BRINGUP = 1) (
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// AXI4 Slave for configuration
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// AXI4 stream slave for source stream (TX_DMA or ADC) -- Source interface
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input s_axis_aclk,
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input s_axis_aresetn,
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output s_axis_ready,
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input s_axis_valid,
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input [SRC_DATA_WIDTH-1:0] s_axis_data,
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input s_axis_last,
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input [SRC_DATA_WIDTH/8-1:0] s_axis_tkeep,
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// AXI4 stream master for destination stream (RX_DMA or DAC) -- Destination
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// interface
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output m_axis_valid,
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output [DST_DATA_WIDTH-1:0] m_axis_data,
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output m_axis_last,
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output [DST_DATA_WIDTH/8-1:0] m_axis_tkeep,
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// initialization request interface
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input init_req,
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output init_ack,
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input sync_ext,
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// FIFO interface - Memory UI
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output fifo_src_wen,
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output fifo_src_resetn,
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output [SRC_ADDR_WIDTH-1:0] fifo_src_waddr,
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output [SRC_DATA_WIDTH-1:0] fifo_src_wdata,
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output fifo_src_wlast,
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output fifo_dst_ren,
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input fifo_dst_ready,
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output fifo_dst_resetn,
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output [DST_ADDR_WIDTH-1:0] fifo_dst_raddr,
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input [DST_DATA_WIDTH-1:0] fifo_dst_rdata,
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// Status and monitor
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input ddr_calib_done
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);
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// local parameters -- to make the code more readable
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localparam SRC_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH > DST_DATA_WIDTH) ? 3 : 3 + $clog2(SRC_DATA_WIDTH/DST_DATA_WIDTH);
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localparam DST_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH <= DST_DATA_WIDTH) ? 3 + $clog2(DST_DATA_WIDTH/SRC_DATA_WIDTH) : 3;
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localparam SRC_BEAT_BYTE = $clog2(SRC_DATA_WIDTH/8);
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// NOTE: Clock domain prefixes
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// src_* - AXI4 Stream Slave interface's clock domain
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// dst_* - AXI4 Stream Master interface's clock domain
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [31:0] up_rdata_s;
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wire src_clk;
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wire src_rstn;
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wire src_valid_out_s;
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wire [SRC_ADDR_WIDTH-1:0] src_wr_addr_s;
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wire src_wr_ready_s;
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wire src_wr_last_s;
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wire [SRC_DATA_WIDTH/8-1:0] src_wr_tkeep_s;
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wire dst_clk;
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wire dst_rstn;
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wire [DST_ADDR_WIDTH-1:0] dst_raddr_s;
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wire [DST_DATA_WIDTH-1:0] dst_mem_data_s;
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wire src_bypass_s;
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wire dst_bypass_s;
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wire oneshot_s;
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wire [63:0] sample_count_s;
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wire [ 1:0] sync_config_s;
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wire sync_int_s;
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wire valid_bypass_s;
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wire [DST_DATA_WIDTH-1:0] data_bypass_s;
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wire ready_bypass_s;
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wire [ 1:0] src_fsm_status_s;
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wire [ 1:0] dst_fsm_status_s;
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wire m_axis_valid_s;
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wire m_axis_last_s;
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wire [DST_DATA_WIDTH-1:0] m_axis_data_s;
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wire dst_mem_valid_s;
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wire dst_mem_valid_int_s;
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wire m_axis_reset_int_s;
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wire [31:0] src_transfer_length_s;
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wire src_wr_last_int_s;
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wire [31:0] src_wr_last_beat_s;
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wire int_not_full;
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assign src_clk = s_axis_aclk;
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assign dst_clk = m_axis_aclk;
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// internal registers
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reg [31:0] src_data_counter = 0;
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reg dst_mem_valid_d = 1'b0;
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generate
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if (TX_OR_RXN_PATH) begin
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assign src_wr_last_s = s_axis_last;
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assign src_wr_tkeep_s = s_axis_tkeep;
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assign m_axis_reset_int_s = ~dst_rstn;
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end else begin
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assign src_wr_last_s = src_wr_last_int_s;
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assign src_wr_tkeep_s = {(SRC_DATA_WIDTH/8){1'b1}};
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assign m_axis_reset_int_s = ~dst_rstn | ~init_req;
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end
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endgenerate
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assign fifo_src_wlast = src_wr_last_s;
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// Offload FSM and control
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data_offload_fsm #(
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.TX_OR_RXN_PATH (TX_OR_RXN_PATH),
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.WR_ADDRESS_WIDTH (SRC_ADDR_WIDTH),
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.WR_DATA_WIDTH (SRC_DATA_WIDTH),
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.RD_ADDRESS_WIDTH (DST_ADDR_WIDTH),
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.RD_DATA_WIDTH (DST_DATA_WIDTH))
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i_data_offload_fsm (
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.wr_clk (src_clk),
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.wr_resetn_in (src_rstn),
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.wr_resetn_out (fifo_src_resetn),
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.wr_valid_in (s_axis_valid),
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.wr_valid_out (fifo_src_wen),
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.wr_ready (src_wr_ready_s),
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.wr_addr (fifo_src_waddr),
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.wr_last (src_wr_last_s),
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.wr_tkeep (src_wr_tkeep_s),
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.rd_clk (dst_clk),
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.rd_resetn_in (dst_rstn),
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.rd_resetn_out (fifo_dst_resetn),
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.rd_ready (fifo_dst_ready_int_s),
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.rd_valid (dst_mem_valid_s),
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.rd_addr (fifo_dst_raddr),
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.rd_last (),
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.rd_tkeep (m_axis_tkeep),
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.rd_oneshot (oneshot_s),
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.init_req (init_req),
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.init_ack (init_ack),
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.sync_config (sync_config_s),
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.sync_external (sync_ext),
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.sync_internal (sync_int_s),
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.wr_fsm_state (src_fsm_status_s),
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.rd_fsm_state (dst_fsm_status_s),
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.sample_count (sample_count_s)
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);
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// In case of external memory, read back can not start right after the write
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// was finished (because of the CDC FIFOs and the latency of the EMIF
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// interface)
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generate
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if (MEM_TYPE == 1'b1) begin
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assign dst_mem_valid_int_s = dst_mem_valid_s;
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end else begin
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// Compensate the 1 cycle READ latency of the BRAM
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always @(posedge m_axis_aclk) begin
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dst_mem_valid_d <= dst_mem_valid_s;
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end
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assign dst_mem_valid_int_s = dst_mem_valid_d;
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end
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endgenerate
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assign fifo_dst_ready_int_s = fifo_dst_ready & int_not_full;
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assign fifo_src_wdata = s_axis_data;
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assign fifo_dst_ren = dst_mem_valid_s;
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ad_axis_inf_rx #(
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.DATA_WIDTH (DST_DATA_WIDTH))
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i_rx_axis_inf (
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.clk (m_axis_aclk),
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.rst (m_axis_reset_int_s),
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.valid (dst_mem_valid_int_s),
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.data (fifo_dst_rdata),
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.last (1'b0),
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.inf_valid (m_axis_valid_s),
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.inf_last (m_axis_last_s),
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.inf_data (m_axis_data_s),
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.inf_ready (m_axis_ready),
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.int_not_full(int_not_full));
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assign m_axis_valid = (dst_bypass_s) ? valid_bypass_s : m_axis_valid_s;
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assign m_axis_data = (dst_bypass_s) ? data_bypass_s : m_axis_data_s;
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assign m_axis_last = (dst_bypass_s) ? 1'b0 : m_axis_last_s;
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assign s_axis_ready = (src_bypass_s) ? ready_bypass_s : src_wr_ready_s;
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// Bypass module instance -- the same FIFO, just a smaller depth
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// NOTE: Generating an overflow is making sense just in BYPASS mode, and
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// it's supported just with the FIFO interface
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util_axis_fifo_asym #(
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.S_DATA_WIDTH (SRC_DATA_WIDTH),
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.S_ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS),
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.M_DATA_WIDTH (DST_DATA_WIDTH),
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.ASYNC_CLK (1))
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i_bypass_fifo (
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.m_axis_aclk (m_axis_aclk),
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.m_axis_aresetn (dst_rstn),
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.m_axis_ready (m_axis_ready),
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.m_axis_valid (valid_bypass_s),
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.m_axis_data (data_bypass_s),
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.m_axis_tlast (),
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.m_axis_empty (),
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.m_axis_almost_empty (),
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.s_axis_aclk (s_axis_aclk),
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.s_axis_aresetn (src_rstn),
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.s_axis_ready (ready_bypass_s),
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.s_axis_valid (s_axis_valid),
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.s_axis_data (s_axis_data),
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.s_axis_tlast (),
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.s_axis_full (),
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.s_axis_almost_full ()
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);
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// register map
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data_offload_regmap #(
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.ID (ID),
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.MEM_TYPE (MEM_TYPE),
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.MEM_SIZE (MEM_SIZE),
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.TX_OR_RXN_PATH (TX_OR_RXN_PATH),
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.AUTO_BRINGUP (AUTO_BRINGUP))
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i_regmap (
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_rreq (up_rreq_s),
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.up_rack (up_rack_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_wreq (up_wreq_s),
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.up_wack (up_wack_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.src_clk (s_axis_aclk),
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.dst_clk (m_axis_aclk),
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.src_sw_resetn (src_rstn),
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.dst_sw_resetn (dst_rstn),
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.ddr_calib_done (ddr_calib_done),
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.src_bypass (src_bypass_s),
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.dst_bypass (dst_bypass_s),
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.oneshot (oneshot_s),
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.sync (sync_int_s),
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.sync_config (sync_config_s),
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.src_transfer_length (src_transfer_length_s),
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.src_fsm_status (src_fsm_status_s),
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.dst_fsm_status (dst_fsm_status_s),
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.sample_count_msb (sample_count_s[63:32]),
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.sample_count_lsb (sample_count_s[31: 0])
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);
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// axi interface wrapper
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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up_axi #(
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.AXI_ADDRESS_WIDTH (16))
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i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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/* Beat counter on the source interface
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*
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* The storage unit can have size of a couple of Gbyte, which in case of an RX
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* path would mean to fill up all that memory space before pushing over the
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* stream to the RX DMA. (ADC can not generate a tlast) To make things more
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* practical, user can set an arbitrary transfer length using the
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* transfer_length register, which will be used to generate an internal tlast
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* signal for the source FSM. If the register is set to zero, all the memory
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* will be filled up, before passing control to the destination FSM.
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*
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*/
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always @(posedge s_axis_aclk) begin
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if (fifo_src_resetn == 1'b0) begin // counter should reset when source FMS resets
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src_data_counter <= 0;
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end else begin
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if (fifo_src_wen & src_wr_ready_s) begin
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src_data_counter <= src_data_counter + 1'b1;
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end
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end
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end
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// transfer length is in bytes, but counter monitors the source data beats
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assign src_wr_last_beat_s = (src_transfer_length_s == 32'h0) ? MEM_SIZE[31:SRC_BEAT_BYTE]-1 : src_transfer_length_s[31:SRC_BEAT_BYTE];
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assign src_wr_last_int_s = (src_data_counter == src_wr_last_beat_s) ? 1'b1 : 1'b0;
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endmodule
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