497 lines
14 KiB
Verilog
Executable File
497 lines
14 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ADC channel-need to work on dual mode for pn sequence
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`timescale 1ns/100ps
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module axi_ad9361_rx (
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// adc interface
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adc_clk,
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adc_valid,
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adc_data_i1,
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adc_data_q1,
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adc_data_i2,
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adc_data_q2,
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adc_lb_enb_i1,
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adc_pn_oos_i1,
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adc_pn_err_i1,
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adc_lb_enb_q1,
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adc_pn_oos_q1,
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adc_pn_err_q1,
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adc_lb_enb_i2,
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adc_pn_oos_i2,
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adc_pn_err_i2,
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adc_lb_enb_q2,
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adc_pn_oos_q2,
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adc_pn_err_q2,
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adc_status,
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adc_r1_mode,
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// delay interface
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delay_clk,
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delay_rst,
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_rdata,
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delay_ack_t,
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delay_locked,
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// dma interface
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adc_chan_i1,
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adc_enable_0,
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adc_valid_0,
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adc_chan_q1,
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adc_enable_1,
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adc_valid_1,
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adc_chan_i2,
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adc_enable_2,
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adc_valid_2,
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adc_chan_q2,
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adc_enable_3,
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adc_valid_3,
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adc_dovf,
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adc_dunf,
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// processor interface
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wdata,
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up_rdata,
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up_ack,
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// monitor signals
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adc_mon_valid,
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adc_mon_data,
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// debug signals
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adc_dbg_trigger,
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adc_dbg_data);
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// parameters
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parameter DP_DISABLE = 0;
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parameter PCORE_ID = 0;
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// adc interface
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input adc_clk;
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input adc_valid;
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input [11:0] adc_data_i1;
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input [11:0] adc_data_q1;
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input [11:0] adc_data_i2;
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input [11:0] adc_data_q2;
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output adc_lb_enb_i1;
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input adc_pn_oos_i1;
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input adc_pn_err_i1;
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output adc_lb_enb_q1;
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input adc_pn_oos_q1;
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input adc_pn_err_q1;
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output adc_lb_enb_i2;
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input adc_pn_oos_i2;
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input adc_pn_err_i2;
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output adc_lb_enb_q2;
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input adc_pn_oos_q2;
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input adc_pn_err_q2;
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input adc_status;
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output adc_r1_mode;
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// delay interface
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input delay_clk;
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output delay_rst;
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output delay_sel;
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output delay_rwn;
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output [ 7:0] delay_addr;
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output [ 4:0] delay_wdata;
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input [ 4:0] delay_rdata;
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input delay_ack_t;
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input delay_locked;
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// dma interface
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output [15:0] adc_chan_i1;
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output adc_enable_0;
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output adc_valid_0;
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output [15:0] adc_chan_q1;
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output adc_enable_1;
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output adc_valid_1;
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output [15:0] adc_chan_i2;
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output adc_enable_2;
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output adc_valid_2;
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output [15:0] adc_chan_q2;
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output adc_enable_3;
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output adc_valid_3;
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input adc_dovf;
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input adc_dunf;
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// processor interface
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input [31:0] up_wdata;
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output [31:0] up_rdata;
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output up_ack;
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// monitor signals
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output adc_mon_valid;
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output [47:0] adc_mon_data;
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// debug signals
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output [ 1:0] adc_dbg_trigger;
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output [116:0] adc_dbg_data;
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// internal registers
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reg adc_iqcor_valid = 'd0;
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reg up_adc_status_pn_err = 'd0;
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reg up_adc_status_pn_oos = 'd0;
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reg up_adc_status_or = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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// internal clocks and resets
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wire adc_rst;
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// internal signals
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wire adc_iqcor_valid_s;
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wire [15:0] adc_dcfilter_data_out_0_s;
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wire adc_pn_oos_out_0_s;
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wire adc_pn_err_out_0_s;
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wire up_adc_pn_err_0_s;
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wire up_adc_pn_oos_0_s;
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wire up_adc_or_0_s;
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wire [31:0] up_rdata_0_s;
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wire up_ack_0_s;
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wire [15:0] adc_dcfilter_data_out_1_s;
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wire up_adc_pn_err_1_s;
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wire up_adc_pn_oos_1_s;
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wire up_adc_or_1_s;
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wire [31:0] up_rdata_1_s;
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wire up_ack_1_s;
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wire [15:0] adc_dcfilter_data_out_2_s;
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wire adc_pn_oos_out_2_s;
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wire adc_pn_err_out_2_s;
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wire up_adc_pn_err_2_s;
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wire up_adc_pn_oos_2_s;
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wire up_adc_or_2_s;
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wire [31:0] up_rdata_2_s;
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wire up_ack_2_s;
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wire [15:0] adc_dcfilter_data_out_3_s;
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wire up_adc_pn_err_3_s;
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wire up_adc_pn_oos_3_s;
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wire up_adc_or_3_s;
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wire [31:0] up_rdata_3_s;
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wire up_ack_3_s;
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wire [31:0] up_rdata_s;
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wire up_ack_s;
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// monitor signals
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assign adc_mon_valid = adc_valid;
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assign adc_mon_data[11: 0] = adc_data_i1;
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assign adc_mon_data[23:12] = adc_data_q1;
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assign adc_mon_data[35:24] = adc_data_i2;
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assign adc_mon_data[47:36] = adc_data_q2;
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// debug signals
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assign adc_dbg_trigger[0] = adc_iqcor_valid_s;
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assign adc_dbg_trigger[1] = adc_valid;
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assign adc_dbg_data[ 15: 0] = adc_chan_i1;
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assign adc_dbg_data[ 31: 16] = adc_chan_q1;
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assign adc_dbg_data[ 47: 32] = adc_chan_i2;
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assign adc_dbg_data[ 63: 48] = adc_chan_q2;
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assign adc_dbg_data[ 64: 64] = adc_valid_0;
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assign adc_dbg_data[ 65: 65] = adc_valid_1;
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assign adc_dbg_data[ 66: 66] = adc_valid_2;
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assign adc_dbg_data[ 67: 67] = adc_valid_3;
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assign adc_dbg_data[ 79: 68] = adc_data_i1;
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assign adc_dbg_data[ 91: 80] = adc_data_q1;
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assign adc_dbg_data[103: 92] = adc_data_i2;
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assign adc_dbg_data[115:104] = adc_data_q2;
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assign adc_dbg_data[116:116] = adc_valid;
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// adc channels - dma interface
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assign adc_iqcor_valid_s = adc_valid_0 & adc_valid_1 &
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adc_valid_2 & adc_valid_3;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_status_pn_err <= 'd0;
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up_adc_status_pn_oos <= 'd0;
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up_adc_status_or <= 'd0;
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up_rdata <= 'd0;
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up_ack <= 'd0;
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end else begin
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up_adc_status_pn_err <= up_adc_pn_err_0_s | up_adc_pn_err_1_s |
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up_adc_pn_err_2_s | up_adc_pn_err_3_s;
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up_adc_status_pn_oos <= up_adc_pn_oos_0_s | up_adc_pn_oos_1_s |
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up_adc_pn_oos_2_s | up_adc_pn_oos_3_s;
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up_adc_status_or <= up_adc_or_0_s | up_adc_or_1_s |
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up_adc_or_2_s | up_adc_or_3_s;
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up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s |
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up_rdata_2_s | up_rdata_3_s;
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up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s |
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up_ack_2_s | up_ack_3_s;
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end
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end
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// channel 0 (i)
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axi_ad9361_rx_channel #(
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.IQSEL(0),
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.CHID(0),
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.DP_DISABLE (DP_DISABLE))
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i_rx_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_pn_oos_pl (adc_pn_oos_i1),
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.adc_pn_err_pl (adc_pn_err_i1),
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.adc_data (adc_data_i1),
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.adc_data_q (adc_data_q1),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
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.adc_pn_oos_out (adc_pn_oos_out_0_s),
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.adc_pn_err_out (adc_pn_err_out_0_s),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
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.adc_pn_oos_in (1'd0),
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.adc_pn_err_in (1'd0),
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.adc_iqcor_valid (adc_valid_0),
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.adc_iqcor_data (adc_chan_i1),
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.adc_enable (adc_enable_0),
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.adc_lb_enb (adc_lb_enb_i1),
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.up_adc_pn_err (up_adc_pn_err_0_s),
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.up_adc_pn_oos (up_adc_pn_oos_0_s),
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.up_adc_or (up_adc_or_0_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_0_s),
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.up_ack (up_ack_0_s));
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// channel 1 (q)
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axi_ad9361_rx_channel #(
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.IQSEL(1),
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.CHID(1),
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.DP_DISABLE (DP_DISABLE))
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i_rx_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_pn_oos_pl (adc_pn_oos_q1),
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.adc_pn_err_pl (adc_pn_err_q1),
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.adc_data (adc_data_q1),
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.adc_data_q (12'd0),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
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.adc_pn_oos_out (),
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.adc_pn_err_out (),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
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.adc_pn_oos_in (adc_pn_oos_out_0_s),
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.adc_pn_err_in (adc_pn_err_out_0_s),
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.adc_iqcor_valid (adc_valid_1),
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.adc_iqcor_data (adc_chan_q1),
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.adc_enable (adc_enable_1),
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.adc_lb_enb (adc_lb_enb_q1),
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.up_adc_pn_err (up_adc_pn_err_1_s),
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.up_adc_pn_oos (up_adc_pn_oos_1_s),
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.up_adc_or (up_adc_or_1_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_1_s),
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.up_ack (up_ack_1_s));
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// channel 2 (i)
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axi_ad9361_rx_channel #(
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.IQSEL(0),
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.CHID(2),
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.DP_DISABLE (DP_DISABLE))
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i_rx_channel_2 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_pn_oos_pl (adc_pn_oos_i2),
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.adc_pn_err_pl (adc_pn_err_i2),
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.adc_data (adc_data_i2),
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.adc_data_q (adc_data_q2),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_2_s),
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.adc_pn_oos_out (adc_pn_oos_out_2_s),
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.adc_pn_err_out (adc_pn_err_out_2_s),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_3_s),
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.adc_pn_oos_in (1'd0),
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.adc_pn_err_in (1'd0),
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.adc_iqcor_valid (adc_valid_2),
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.adc_iqcor_data (adc_chan_i2),
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.adc_enable (adc_enable_2),
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.adc_lb_enb (adc_lb_enb_i2),
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.up_adc_pn_err (up_adc_pn_err_2_s),
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.up_adc_pn_oos (up_adc_pn_oos_2_s),
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.up_adc_or (up_adc_or_2_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
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.up_wr (up_wr),
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.up_addr (up_addr),
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.up_wdata (up_wdata),
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.up_rdata (up_rdata_2_s),
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.up_ack (up_ack_2_s));
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// channel 3 (q)
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axi_ad9361_rx_channel #(
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.IQSEL(1),
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.CHID(3),
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.DP_DISABLE (DP_DISABLE))
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i_rx_channel_3 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_pn_oos_pl (adc_pn_oos_q2),
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.adc_pn_err_pl (adc_pn_err_q2),
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.adc_data (adc_data_q2),
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.adc_data_q (12'd0),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_3_s),
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.adc_pn_oos_out (),
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.adc_pn_err_out (),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_2_s),
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.adc_pn_oos_in (adc_pn_oos_out_2_s),
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.adc_pn_err_in (adc_pn_err_out_2_s),
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.adc_iqcor_valid (adc_valid_3),
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.adc_iqcor_data (adc_chan_q2),
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.adc_enable (adc_enable_3),
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.adc_lb_enb (adc_lb_enb_q2),
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.up_adc_pn_err (up_adc_pn_err_3_s),
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.up_adc_pn_oos (up_adc_pn_oos_3_s),
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.up_adc_or (up_adc_or_3_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel),
|
|
.up_wr (up_wr),
|
|
.up_addr (up_addr),
|
|
.up_wdata (up_wdata),
|
|
.up_rdata (up_rdata_3_s),
|
|
.up_ack (up_ack_3_s));
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|
|
|
// common processor control
|
|
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|
up_adc_common #(.PCORE_ID (PCORE_ID)) i_up_adc_common (
|
|
.mmcm_rst (),
|
|
.adc_clk (adc_clk),
|
|
.adc_rst (adc_rst),
|
|
.adc_r1_mode (adc_r1_mode),
|
|
.adc_ddr_edgesel (),
|
|
.adc_pin_mode (),
|
|
.adc_status (adc_status),
|
|
.adc_status_pn_err (up_adc_status_pn_err),
|
|
.adc_status_pn_oos (up_adc_status_pn_oos),
|
|
.adc_status_or (up_adc_status_or),
|
|
.adc_status_ovf (adc_dovf),
|
|
.adc_status_unf (adc_dunf),
|
|
.adc_clk_ratio (32'd1),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_sel (delay_sel),
|
|
.delay_rwn (delay_rwn),
|
|
.delay_addr (delay_addr),
|
|
.delay_wdata (delay_wdata),
|
|
.delay_rdata (delay_rdata),
|
|
.delay_ack_t (delay_ack_t),
|
|
.delay_locked (delay_locked),
|
|
.drp_clk (1'd0),
|
|
.drp_rst (),
|
|
.drp_sel (),
|
|
.drp_wr (),
|
|
.drp_addr (),
|
|
.drp_wdata (),
|
|
.drp_rdata (16'd0),
|
|
.drp_ready (1'd0),
|
|
.drp_locked (1'd1),
|
|
.up_usr_chanmax (),
|
|
.adc_usr_chanmax (8'd3),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_sel),
|
|
.up_wr (up_wr),
|
|
.up_addr (up_addr),
|
|
.up_wdata (up_wdata),
|
|
.up_rdata (up_rdata_s),
|
|
.up_ack (up_ack_s));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|