222 lines
7.0 KiB
Verilog
Executable File
222 lines
7.0 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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`timescale 1ns/100ps
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module axi_ad9361_pnlb (
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// interface - inputs
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clk,
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adc_valid_in,
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adc_data_in_i1,
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adc_data_in_q1,
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adc_data_in_i2,
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adc_data_in_q2,
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dac_valid_in,
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dac_data_in_i1,
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dac_data_in_q1,
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dac_data_in_i2,
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dac_data_in_q2,
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// interface - outputs
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adc_valid,
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adc_data_i1,
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adc_data_q1,
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adc_data_i2,
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adc_data_q2,
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dac_valid,
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dac_data_i1,
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dac_data_q1,
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dac_data_i2,
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dac_data_q2,
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// control signals
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adc_lb_enb_i1,
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dac_lb_enb_i1,
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dac_pn_enb_i1,
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adc_lb_enb_q1,
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dac_lb_enb_q1,
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dac_pn_enb_q1,
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adc_lb_enb_i2,
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dac_lb_enb_i2,
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dac_pn_enb_i2,
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adc_lb_enb_q2,
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dac_lb_enb_q2,
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dac_pn_enb_q2,
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// status signals
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adc_pn_oos_i1,
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adc_pn_err_i1,
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adc_pn_oos_q1,
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adc_pn_err_q1,
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adc_pn_oos_i2,
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adc_pn_err_i2,
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adc_pn_oos_q2,
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adc_pn_err_q2);
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// device interface
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input clk;
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input adc_valid_in;
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input [11:0] adc_data_in_i1;
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input [11:0] adc_data_in_q1;
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input [11:0] adc_data_in_i2;
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input [11:0] adc_data_in_q2;
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input dac_valid_in;
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input [11:0] dac_data_in_i1;
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input [11:0] dac_data_in_q1;
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input [11:0] dac_data_in_i2;
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input [11:0] dac_data_in_q2;
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// dac outputs
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output adc_valid;
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output [11:0] adc_data_i1;
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output [11:0] adc_data_q1;
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output [11:0] adc_data_i2;
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output [11:0] adc_data_q2;
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output dac_valid;
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output [11:0] dac_data_i1;
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output [11:0] dac_data_q1;
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output [11:0] dac_data_i2;
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output [11:0] dac_data_q2;
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// control signals
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input adc_lb_enb_i1;
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input dac_lb_enb_i1;
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input dac_pn_enb_i1;
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input adc_lb_enb_q1;
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input dac_lb_enb_q1;
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input dac_pn_enb_q1;
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input adc_lb_enb_i2;
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input dac_lb_enb_i2;
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input dac_pn_enb_i2;
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input adc_lb_enb_q2;
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input dac_lb_enb_q2;
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input dac_pn_enb_q2;
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// status signals
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output adc_pn_oos_i1;
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output adc_pn_err_i1;
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output adc_pn_oos_q1;
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output adc_pn_err_q1;
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output adc_pn_oos_i2;
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output adc_pn_err_i2;
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output adc_pn_oos_q2;
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output adc_pn_err_q2;
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// instantiations
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axi_ad9361_pnlb_1 #(.PRBS_SEL(0)) i_pnlb_i1 (
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.clk (clk),
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.adc_valid_in (adc_valid_in),
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.adc_data_in (adc_data_in_i1),
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.dac_valid_in (dac_valid_in),
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.dac_data_in (dac_data_in_i1),
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.adc_valid (adc_valid),
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.adc_data (adc_data_i1),
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.dac_valid (dac_valid),
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.dac_data (dac_data_i1),
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.adc_lb_enb (adc_lb_enb_i1),
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.dac_lb_enb (dac_lb_enb_i1),
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.dac_pn_enb (dac_pn_enb_i1),
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.adc_pn_oos (adc_pn_oos_i1),
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.adc_pn_err (adc_pn_err_i1));
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axi_ad9361_pnlb_1 #(.PRBS_SEL(1)) i_pnlb_q1 (
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.clk (clk),
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.adc_valid_in (adc_valid_in),
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.adc_data_in (adc_data_in_q1),
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.dac_valid_in (dac_valid_in),
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.dac_data_in (dac_data_in_q1),
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.adc_valid (),
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.adc_data (adc_data_q1),
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.dac_valid (),
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.dac_data (dac_data_q1),
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.adc_lb_enb (adc_lb_enb_q1),
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.dac_lb_enb (dac_lb_enb_q1),
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.dac_pn_enb (dac_pn_enb_q1),
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.adc_pn_oos (adc_pn_oos_q1),
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.adc_pn_err (adc_pn_err_q1));
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axi_ad9361_pnlb_1 #(.PRBS_SEL(2)) i_pnlb_i2 (
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.clk (clk),
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.adc_valid_in (adc_valid_in),
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.adc_data_in (adc_data_in_i2),
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.dac_valid_in (dac_valid_in),
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.dac_data_in (dac_data_in_i2),
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.adc_valid (),
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.adc_data (adc_data_i2),
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.dac_valid (),
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.dac_data (dac_data_i2),
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.adc_lb_enb (adc_lb_enb_i2),
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.dac_lb_enb (dac_lb_enb_i2),
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.dac_pn_enb (dac_pn_enb_i2),
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.adc_pn_oos (adc_pn_oos_i2),
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.adc_pn_err (adc_pn_err_i2));
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axi_ad9361_pnlb_1 #(.PRBS_SEL(3)) i_pnlb_q2 (
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.clk (clk),
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.adc_valid_in (adc_valid_in),
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.adc_data_in (adc_data_in_q2),
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.dac_valid_in (dac_valid_in),
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.dac_data_in (dac_data_in_q2),
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.adc_valid (),
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.adc_data (adc_data_q2),
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.dac_valid (),
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.dac_data (dac_data_q2),
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.adc_lb_enb (adc_lb_enb_q2),
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.dac_lb_enb (dac_lb_enb_q2),
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.dac_pn_enb (dac_pn_enb_q2),
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.adc_pn_oos (adc_pn_oos_q2),
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.adc_pn_err (adc_pn_err_q2));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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