98 lines
2.9 KiB
Verilog
98 lines
2.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_clkdiv (
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input clk,
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input clk_sel,
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output clk_out
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);
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parameter SIM_DEVICE = "7SERIES";
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parameter SEL_0_DIV = "4";
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parameter SEL_1_DIV = "2";
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wire clk_div_sel_0_s;
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wire clk_div_sel_1_s;
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generate if (SIM_DEVICE == "7SERIES") begin
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BUFR #(
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.BUFR_DIVIDE(SEL_0_DIV),
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.SIM_DEVICE("7SERIES")
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) clk_divide_sel_0 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_0_s));
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BUFR #(
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.BUFR_DIVIDE(SEL_1_DIV),
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.SIM_DEVICE("7SERIES")
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) clk_divide_sel_1 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_1_s));
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end else if (SIM_DEVICE == "ULTRASCALE") begin
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE(SEL_0_DIV)
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) clk_divide_sel_0 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_0_s));
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE(SEL_1_DIV)
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) clk_divide_sel_1 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_sel_1_s));
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end endgenerate
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BUFGMUX_CTRL i_div_clk_gbuf (
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.I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
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.I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
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.S(clk_sel),
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.O (clk_out));
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endmodule
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