321 lines
9.2 KiB
Verilog
321 lines
9.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9963_rx #(
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// parameters
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parameter USERPORTS_DISABLE = 0,
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parameter DATAFORMAT_DISABLE = 0,
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parameter DCFILTER_DISABLE = 0,
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parameter IQCORRECTION_DISABLE = 0,
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parameter SCALECORRECTION_ONLY = 1,
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parameter IODELAY_ENABLE = 0,
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0
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) (
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// adc interface
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output adc_rst,
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input adc_clk,
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input adc_valid,
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input [23:0] adc_data,
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input adc_status,
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// delay interface
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output [12:0] up_dld,
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output [64:0] up_dwdata,
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input [64:0] up_drdata,
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input delay_clk,
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output delay_rst,
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input delay_locked,
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// dma interface
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output adc_enable_i,
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output adc_valid_i,
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output [15:0] adc_data_i,
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output adc_enable_q,
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output adc_valid_q,
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output [15:0] adc_data_q,
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input adc_dovf,
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output up_adc_ce,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack
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);
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// configuration settings
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localparam CONFIG = (SCALECORRECTION_ONLY * 512) +
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(0 * 16) +
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(USERPORTS_DISABLE * 8) +
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(DATAFORMAT_DISABLE * 4) +
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(DCFILTER_DISABLE * 2) +
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(IQCORRECTION_DISABLE * 1);
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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// internal signals
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wire [15:0] adc_dcfilter_data_out_0_s;
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wire [15:0] adc_dcfilter_data_out_1_s;
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wire [ 1:0] up_adc_pn_err_s;
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wire [ 1:0] up_adc_pn_oos_s;
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wire [ 1:0] up_adc_or_s;
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wire [31:0] up_rdata_s[0:3];
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wire up_rack_s[0:3];
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wire up_wack_s[0:3];
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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end else begin
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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end
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end
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always @(*) begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
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end
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// channel 0 (i)
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axi_ad9963_rx_channel #(
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.Q_OR_I_N(0),
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.CHANNEL_ID(0),
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.USERPORTS_DISABLE (USERPORTS_DISABLE),
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.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE (DCFILTER_DISABLE),
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.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
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.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
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) i_rx_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_data (adc_data[11:0]),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
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.adc_iqcor_valid (adc_valid_i),
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.adc_iqcor_data (adc_data_i),
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.adc_enable (adc_enable_i),
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.up_adc_pn_err (up_adc_pn_err_s[0]),
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.up_adc_pn_oos (up_adc_pn_oos_s[0]),
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.up_adc_or (up_adc_or_s[0]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// channel 1 (q)
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axi_ad9963_rx_channel #(
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.Q_OR_I_N(1),
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.CHANNEL_ID(1),
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.USERPORTS_DISABLE (USERPORTS_DISABLE),
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.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
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.DCFILTER_DISABLE (DCFILTER_DISABLE),
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.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
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.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY)
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) i_rx_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid),
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.adc_data (adc_data[23:12]),
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.adc_or (1'b0),
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.adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
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.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
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.adc_iqcor_valid (adc_valid_q),
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.adc_iqcor_data (adc_data_q),
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.adc_enable (adc_enable_q),
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.up_adc_pn_err (up_adc_pn_err_s[1]),
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.up_adc_pn_oos (up_adc_pn_oos_s[1]),
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.up_adc_or (up_adc_or_s[1]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// common processor control
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up_adc_common #(
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.ID (ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.CONFIG (CONFIG),
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.COMMON_ID(6'h00),
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.DRP_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.GPIO_DISABLE (1),
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.START_CODE_DISABLE (1)
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) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status),
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.adc_sync_status (1'd0),
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.adc_status_ovf (adc_dovf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.adc_ext_sync_arm (),
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.adc_ext_sync_disarm (),
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.adc_ext_sync_manual_req (),
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.adc_num_lanes (),
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.adc_custom_control (),
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.adc_crc_enable (),
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.adc_sdr_ddr_n (),
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.adc_symb_op (),
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.adc_symb_8_16b (),
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.up_pps_rcounter(32'h0),
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.up_pps_status(1'b0),
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.up_pps_irq_mask(),
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.up_adc_r1_mode (),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (16'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax_out (),
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.adc_config_wr (),
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.adc_config_ctrl (),
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.adc_config_rd ('d0),
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.adc_ctrl_status ('d0),
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.up_usr_chanmax_in (8'd1),
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.up_adc_gpio_in (32'h0),
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.up_adc_gpio_out (),
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.up_adc_ce(up_adc_ce),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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// adc delay control
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generate if (IODELAY_ENABLE == 1) begin
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up_delay_cntrl #(
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.DATA_WIDTH(13),
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.BASE_ADDRESS(6'h02)
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) i_delay_cntrl (
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked),
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.up_dld (up_dld),
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.up_dwdata (up_dwdata),
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.up_drdata (up_drdata),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack_s[3]),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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end else begin
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assign up_dld = 'h00;
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assign up_dwdata = 'h00;
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assign delay_rst = 1'b1;
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assign up_wack_s[3] = 0;
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assign up_rack_s[3] = 0;
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assign up_rdata_s[3] = 'h00;
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end
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endgenerate
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endmodule
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