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Dan Hotoleanu e8ff32d6df ad6676evb: Parameterize JESD204 configuration values 
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
 		2022-01-31 10:36:31 +02:00
..
Makefile ad6676evb: Update to JESD204 TPL instantiation 2022-01-31 10:36:31 +02:00
system_bd.tcl sysid: Upgrade framework, header/ip are now at 2/1.1.a 2021-01-20 01:02:56 +02:00
system_constr.xdc jesd_rst_gen:constraints: Remove invalid false path definitions 2018-04-11 15:09:54 +03:00
system_project.tcl ad6676evb: Parameterize JESD204 configuration values 2022-01-31 10:36:31 +02:00
system_top.v ad6676evb: Parameterize JESD204 configuration values 2022-01-31 10:36:31 +02:00