153 lines
3.9 KiB
Verilog
153 lines
3.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module dmac_dest_fifo_inf #(
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parameter ID_WIDTH = 3,
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parameter DATA_WIDTH = 64,
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parameter BEATS_PER_BURST_WIDTH = 4)(
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input clk,
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input resetn,
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input enable,
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output enabled,
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input sync_id,
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output sync_id_ret,
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input [ID_WIDTH-1:0] request_id,
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output [ID_WIDTH-1:0] response_id,
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output [ID_WIDTH-1:0] data_id,
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input data_eot,
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input response_eot,
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input en,
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output [DATA_WIDTH-1:0] dout,
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output valid,
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output underflow,
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output xfer_req,
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output fifo_ready,
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input fifo_valid,
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input [DATA_WIDTH-1:0] fifo_data,
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input req_valid,
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output req_ready,
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input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
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output response_valid,
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input response_ready,
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output response_resp_eot,
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output [1:0] response_resp
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);
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assign sync_id_ret = sync_id;
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wire data_enabled;
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wire _fifo_ready;
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assign fifo_ready = _fifo_ready | ~enabled;
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reg en_d1;
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wire data_ready;
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wire data_valid;
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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en_d1 <= 1'b0;
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end else begin
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en_d1 <= en;
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end
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end
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assign underflow = en_d1 & (~data_valid | ~enable);
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assign data_ready = en_d1 & (data_valid | ~enable);
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assign valid = en_d1 & data_valid & enable;
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dmac_data_mover # (
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.ID_WIDTH(ID_WIDTH),
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.DATA_WIDTH(DATA_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
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.DISABLE_WAIT_FOR_ID(0)
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) i_data_mover (
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.clk(clk),
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.resetn(resetn),
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.enable(enable),
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.enabled(data_enabled),
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.sync_id(sync_id),
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.xfer_req(xfer_req),
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.request_id(request_id),
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.response_id(data_id),
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.eot(data_eot),
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.req_valid(req_valid),
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.req_ready(req_ready),
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.req_last_burst_length(req_last_burst_length),
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.s_axi_ready(_fifo_ready),
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.s_axi_valid(fifo_valid),
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.s_axi_data(fifo_data),
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.m_axi_ready(data_ready),
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.m_axi_valid(data_valid),
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.m_axi_data(dout),
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.m_axi_last()
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);
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dmac_response_generator # (
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.ID_WIDTH(ID_WIDTH)
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) i_response_generator (
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.clk(clk),
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.resetn(resetn),
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.enable(data_enabled),
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.enabled(enabled),
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.sync_id(sync_id),
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.request_id(data_id),
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.response_id(response_id),
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.eot(response_eot),
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.resp_valid(response_valid),
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.resp_ready(response_ready),
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.resp_eot(response_resp_eot),
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.resp_resp(response_resp)
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);
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endmodule
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